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Questions tagged [system-verilog]

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.

It is defined by IEEE 1800-2012 and with the exception of some keywords, is a backwards-compatible superset of , IEEE 1364-2005.

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Why don't I see the clocking block input skew in waveforms?

That's the code: module flipflop (input logic clk, reset, input logic [7:0] qin, output logic [7:0] qout); timeunit 1ns; always @(posedge clk or posedge reset) if (reset) qout = '0; else qout =…
Chengineer
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Nonblocking ++ equivalent in SystemVerilog

The ++ operator in Systemverilog is blocking. Is there a nonblocking equivalent to it, or are we bound to use the more verbose x<=x+1 form if we want to keep it nonblocking? Refer to IEEE Std 1800-2017, section 11.4.2 Increment and decrement…
shaiko
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System Verilog seq.ended or seq.triggered

Some verification tools support the following System Verilog code: wire s = seq.ended; Where seq is an SVA sequence. Other tools do not support this code. Is this "standard SV"? If not, what would be an equivalent way to define such a wire in…
Avner Landver
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How to get a random seed value at that randomize simulation time in SystemVerilog?

I know 3 EDA companies handle with SVSEED as the below image, For reproducibility and random stability, I'd like to generate a random value by using "+svseed random" in SystemVerilog Cadence simulation as the below example snippet code, class…
Carter
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Correctly printing from SystemVerilog DPI

I have some verilog VPI code that I'm porting to use SystemVerilog DPI, to be run in Modelsim and Verilator. In VPI, I use vpi_printf() for debugging and status information. This doesn't work when running the DPI in Verilator. Should I just be using…
pjc50
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Continuous assignment during SystemVerilog simulation

I am providing input to an SPI interface. The input signal is a concatenation of several different signals. What I would like to do in simulation is have continuous concatenation of the different signals into one final string that will be sent to…
Unreasonable Sin
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What happens when the number of bits required to represent possible values in constraint (var inside {[x:y]};) exceed the rand variable width?

For the following class: class CPacket; int offset; rand bit [3:0] sa, da; int lo = 2, hi = 10; constraint LimitA { sa inside {[lo:hi]}; da inside {[lo:hi]}; } function void pre_randomize(); if(this.offset) begin lo =…
Chengineer
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Is it possible to make hierarchy of constants in System Verilog?

Is it possible to make a synthesizable hierarchy of constants in System Verilog? For example: There is a board with FPGA and several peripheral ICs. Each IC have some setting registers. Each setting register has a number of parts. And each part…
Arseniy
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what is the difference between logic,reg and wire in system verilog?? explaination with an example would be helpful

explanation with an example would be helpful.i tried:- input logic [9:0] data1 as the input of the counter and loaded this value into the count1 (logic [9:0] count;) and then assigned count1<=data1; at the time when load was 1. but it shows some…
Tania Kapoor
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Is event control iff in systemverilog the same like clock gating?

I have found like this code. Always @(posedge clk iff rst==0 or posedge rst) I think above code like clock gating code. As I know , when rst is 1 then this block is never triggered. So in other word, if I make rst 0 then the block is working. But…
smith Lee
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System-verilog generate module instances and pass input/process output data

I wrote a module in System Verilog, I need 32 modules, so I am using generate statement for instantiation. The problem is that in every rising edge of clock I need to instantiate new values to the modules and then need to choose one of them (in the…
Matt. St
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Instantiating Parameterized Modules in SystemVerilog

In SystemVerilog I would love to instantiate modules like const int primeArray [11] = '{3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37}; logic clock, reset, increment; logic [10:0] match; generate genvar n; for (n = 0; n < 11; n++) begin …
Unreasonable Sin
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Random number generation

I have written this code in system verilog to generate fifty 12-bit random numbers and write them to a file. How can I generate the random numbers in octal instead of decimal? Also, how can I make the numbers display on different lines? Currently,…
priyanka
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Instantiating multidimensional array in system verilog

I want to create an array in systemverilog which has n entries of m bits. logic [n-1:0] arr [m-1:0]; (a) Is this the right way to do it? What if I change the order of placement of the range? Eg. logic arr [n-1:0] [m-1:0]; (b) Does it represent the…
Vaibhav Sundriyal
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How to indicate a constant to a surrounding module

I have a SystemVerilog module that calculates a constant. How can I make this constant available to an enclosing module? Parameters are good for passing constants into a submodule, but they don't seem appropriate for passing constants out of a…
Spices
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