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Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.

Verilog is turned into logic through a process called synthesis. When targeting synthesis (rather than testbench code or esoteric use cases), a sub-set of the full language features will be used since the language can express features which do not map directly to physical gates.

Verilog can be used for many applications, from FPGA implementations, to ASIC design. The application can have a profound impact on how Verilog can be used.

Sometimes it is referred to as Verilog HDL. However it is not the same as VHDL.

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Difference between blocking and nonblocking assignment Verilog

I was reading this page http://www.asic-world.com/verilog/verilog_one_day3.html when I came across the following: We normally have to reset flip-flops, thus every time the clock makes the transition from 0 to 1 (posedge), we check if reset is…
Void Star
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What is the "+:" operator called in Verilog?

I am going through a Verilog test case, and I found this statement: assign XYZ = PQR_AR[44*8 +: 64]; What is the "+:" operator known as? I tried to find this on google, but I didn't get any relevant answer.
shailendra
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Verilog: XOR all signals of vector together

Say I'm given a vector wire large_bus[63:0] of width 64. How can I XOR the individual signals together without writing them all out: assign XOR_value = large_bus[0] ^ large_bus[1] ^ ... ^ large_bus[63] ? I'm especially interested in doing this for…
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Concatenate signal n times in Verilog

Given a signal wire [7:0] dummy, how can I concatenate it n times? That is, is there a notation for the following: {dummy, ..., dummy} // n times ?
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what is the meaning of the pipe symbol "|" in front of a variable

I am analysing some verilog code and found something like wire z = |a & b; while simultation the code behaves just like wire z = a & b; so i was wondering what is the meaning of the | (pipe) symbol? Does it have any impact on the…
Ulli
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Is there a way of conditionally triggering a compile-time error in verilog?

I have a parameterised module in verilog, where the parameters are a clock rate and refresh rate, which is used to calculate how many cycles of inactivity are inserted between instances of a repeating operation. However, it is very easy to set…
Jules
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How to truncate an expression bit width in Verilog?

Consider an expression like: assign x = func(A) ^ func(B); where the output of the func is 32 bits wide, and x is a wire of 16 bits. I want to assign only the lowest 16 bits of the resulting xor. I know the above code already does that, but it also…
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How to compare two numbers (nets, variables, constants) in Verilog

I am new to Verilog, and would like to learn how to compare two numbers. For example, let's compare a parameter or reg (say a) with the number 2 (2'b10). How this will be written in Verilog?
Sherby
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Lint tool is throwing an error about bit width when adding two 10-bit unsigned numbers and assigning to a 11-bit net

My code: module adder(a,b,result); input wire [9:0] a,b; output wire [10:0] result; assign result = a + b; endmodule My company recently changed policy to escalate the linting rule (W164a and W164b) mismatch of LHS and RHS bit widths from…
nebuchadnezzar_II
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How are Verilog "always" statements implemented in hardware?

The Verilog always statement, namely always @(/* condition */) /* block of code */ executes the block of code whenever condition is satisfied. How is such an always block implemented in hardware?
Randomblue
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Procedural blocks in verilog

We have two types of procedural blocks in verilog: initial and always block. The statements inside these blocks are executed sequentially. Does that affect the timing of these signals? For example, in the code below: initial begin a = 1'b0; b =…
sarthak
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Generate an n bit random number in Verilog

I can easily generate a random number of width 32 bits in Verilog using $random. Is there a way to generate a random number of exactly n bits (say n = 70)? I guess I could concatenate many 32-bits random numbers, and then restrict down to the…
Randomblue
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can verilog do `if defined(SOMETHING) ... `elsif defined(SOMETHING_ELSE) ... `endif?

I'm pretty sure I've done something like this in C before where I have a variety of choices but only one will be true at compile, and I'd like to do it for Verilog sims as well. I haven't found anything about it though. Here's what I'd like to…
billt
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Why can't regs be assigned to multiple always blocks in synthesizable Verilog?

The accepted answer to this question notes that "every reg variable can only be assigned to in at most one always statement". It's clear that in a lot of cases assigning a reg to multiple always blocks is meaningless. However, it's seems that there…
Randomblue
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Is it right to initialize a reg in verilog and apply condition with initial value of reg in Verilog?

I have the little doubt related to initializing condition in Verilog. Like in given statement: module rf(out1,ack,en,a,f,c,d,e,clka); input [7:0] a,f,c,d,e; input clka, en; output reg [7:0] out1; output reg ack; reg[7:0] b[1:5]; reg…
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