I know 3 EDA companies handle with SVSEED as the below image,
For reproducibility and random stability, I'd like to generate a random value by using "+svseed random" in SystemVerilog Cadence simulation as the below example snippet code,
class const_c;
rand bit [7:0] a;
...
endclass
module test;
...
const_c cons;
cons = new();
initial begin
for(...) begin
cons.randomize();
printf("Current SVSEED: %0d", ?);
end
end
endmodule
How do we know "svseed" value when "-svseed random" used. it's value in SystemVerilog?