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Some verification tools support the following System Verilog code:

wire s = seq.ended;

Where seq is an SVA sequence. Other tools do not support this code. Is this "standard SV"?

If not, what would be an equivalent way to define such a wire in "standard SV"?

PeterJ
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Avner Landver
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1 Answers1

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Based on the IEEE Std 1800-2005, ended is used inside an assertion, property, or another sequence (§ 17.7.10, ex @(posedge clk) reset ##1 inst ##1 my_seq.ended). triggered is is the equivalent to ended and is allowed outside of an assertion (§ 10.11, ex wait(my_seq.triggered)).

ended has been depreciated in IEEE Std 1800-2012 as mentioned in § C.2.3:

IEEE Std 1800-2005 17.7.3 required using the sequence method ended in sequence expressions and the sequence method triggered in other contexts. Since these two constructs have the same meaning but mutually exclusive usage contexts, in this version of the standard, the triggered method is allowed to be used in sequence expressions, and the usage of ended is deprecated and does not appear in this version of the standard.

Few if any simulators are 1800-2012 complaint, so follow with 1800-2005 for now.

Greg
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