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explanation with an example would be helpful.i tried:- input logic [9:0] data1 as the input of the counter and loaded this value into the count1 (logic [9:0] count;) and then assigned count1<=data1; at the time when load was 1. but it shows some error.

Tania Kapoor
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There is absolutely no difference between reg and logic in SystemVerilog except for the way they are spelled - they are keyword synonyms. logic is meant to replace reg because reg was originally intended to be short for register. Also note that logic is a data type for a signal, whereas wire is a signal type. Another signal type is a variable.

See this post for a more complete explanation.

Seth P
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dave_59
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  • It is totally wrong to say that there is absolutely NO difference between the two. There are many limitations a logic pose. The major difference is that logic will not allow multiple drivers to drive a single variable at the same time and the simulator throws an error. This feature was introduced in SV to ensure that no Write-Write Race takes place. – Vidushi Bajpai Mar 17 '18 at 10:19
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    @VidushiBajpai I stand by my answer. Show me a piece of code that works using one type and not with the other – dave_59 Mar 17 '18 at 21:17
  • @dave_59 There is a lexical restriction on the reg keyword, see §6.7.1 LRM 1800-2017. A net type keyword directly followed by reg keyword is not allowed. E.g. wire reg is not allowed, tri reg is not allowed, ... – HKOB Sep 12 '18 at 04:15