Random number generation

Question

I have written this code in system verilog to generate fifty 12-bit random numbers and write them to a file.

How can I generate the random numbers in octal instead of decimal?

Also, how can I make the numbers display on different lines? Currently, my numbers are being displayed one after the other.

module stimulus_gen();
  class stim_gen;
    rand bit [11:0] addr;
  endclass

  integer file;
  stim_gen obj;

  initial begin
    file = $fopen("input.txt", "w");
    while (!$feof(file))
    begin
     for (int i=0; i<50; i++)
     begin
       obj = new();
       assert(obj.randomize())
       else $fatal(0, "stim_gen::randomize failed");
       //transmit(obj);
       $fwrite(file, obj);
     end
   end
   $fclose(file);
 end
endmodule

You are writing a file, so while (!$feof(file)) will be an infinite loop. Also $fwrite(file, obj); will write the memory address of the object, not the objects addr. — Greg, Jun 11 '14 at 18:09
Please use a regular if statement instead of using an assert. This keeps the assertion coverage reports specific to the verification of your design, not for debugging your testbench. Also, some tools will not execute the expression inside an immediate assertion of you globally disable assertions. Sometime people do that for performance when debugging. — dave_59, Jun 12 '14 at 01:39

Greg · Accepted Answer · 2017-12-18T21:13:27.493

$fwrite(file, obj); will print the memory address of the object. To print the object's addr in oct (followed by a newline), use $fwrite(file, "%o\n", obj.addr); or $fdisplay(file, "%o", obj.addr);

There are also the system display tasks $fwriteo and $fdisplayo which have the default formatting as oct.

This is all well document in IEEE Std 1800-2012 § 21 Input/output system tasks and system functions, as well as previous version of SystemVerilog and all version of Verilog (IEEE Std 1364) in there respected sections on system task/function.

Random number generation

1 Answers1