Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [pll]

PLL is short for "Phase Locked Loop". A PLL is a circuit that is able to keep a local (voltage controlled) oscillator synchronized with an independent given signal frequency.

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PLL - why compare phases not frequencies

I have a question about PLL's. The aim of PLL is to get two signals with the same frequencies (there can be a shift in phases, as I understand). So, in this case, why do you use a phase detector to compare phases, and NOT just compare…
mbes
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What is the difference between first order, second order and third order phase locked loops?

What does PLL order represent? What are the disadvantages in order 1 & 2 PLL comprared to order 3? How to choose the pll type for an application like QPSK demodulator?
Aparna B
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Why do we need phase-locked loops?

I'm very confused about why we need phase-locked loops. On ScienceDirect.com, it reads: Phase-locked loops (PLLs) have many applications in the communications world. The main purpose of a PLL circuit is to synchronize an output oscillator signal…
user3094631
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How do I use a PLL to multiply the input frequency by an irrational number?

For integer multiples, I can use a frequency divider after the VCO to get a multiple of the input frequency. But how do I multiply the input frequency by an irrational number, say \$\sqrt2\$?
In78
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What does the input to output ratio for a PLL chip mean?

For PLL chips, digikey notes the "Ratio - Input:Output". For example, here are two 74HCT4046 ICs: This TI chip has a "Ratio - Input:Output" of "1:4" This NXP chip has a "Ratio - Input:Output" of "2:3" What does this "Ratio - Input:Output"…
lnmaurer
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PLL loop bandwidth, lock time and jitter

For a PLL in short, 1) What controls loop bandwidth? 2) What impact does it have on output phase noise/jitter? 3) What impact does loop bandwidth have on PLL lock time? I am trying to find answers to these questions, could you help?
quantum231
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Can I use a PLL to generate the *phase* component of an SSB signal?

I want to use Kahn's method of Envelope Elimination and Restoration (EER) to produce a single-sideband, supressed-carrier (SSB) signal. Kahn simply clipped a low-level SSB signal, but I wonder if it isn't possible to use a PLL in this…
Brian K1LI
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How can I generate a frequency of 5 GHZ with a crystal

How can I generate a frequency of 5 GHZ with a crystal
user3642
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Function of pll?

What is the relationship between input phase and output phase of a pll(phase locked loop)? Why is it called phase locked? Does it keeps/locks output phase to phase of input meaning output has same phase as input?
DSP_CS
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Simulation of PLL

I am simulating a PLL with a reference frequency of 25 MHz, VCO freq of 450 MHz. I want to plot the gain versus frequency offset of the closed loop PLL in cadence. How should I give the inputs to get the offset frequencies and how should I plot the…
Swap
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orthogonal singal generator

I am working on a single phase PLL (phase locked loop) and I would like to make a phase shift by using orthogonal signal generator non frequency dependent. I have found many method like transport delay, inverse park transformation, Hilbert…
Fadi
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will two plls wander with shared reference clock

I'm trying to learn about pll wander or drift. My reading leads me to believe one of the reasons plls were developed was to fight wander so maybe it does not affect plls? Although I've seen some things about the wander of the source becoming the…
confused
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CD74HC4046 PLL slipping with off-air reference frequency

I am trying to use the Radio 4 198kHz carrier frequency to discipline a PLL, in order to generate a pulse-per-second (PPS) output that is stable over several hours. The issue I am facing is that the PLL slips. Every few seconds it locks on to the…
user
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PLL design VCO and RC filter connection in real sense and not in block diagram level

The above give basic block diagram of PLL, but according to my understanding after the output of Charge pump with loop filter , VC ie the control source for the VCO is connected to which part of the circuit design of the basic VCO (based on cross…
negative_feedback
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Approach to an unknown orthogonal Beta Signal with a known alfa in single phase dq transformation

I am trying to implement a PLL controller to the MCU for tracking single phase line voltage . I get samples via an opamp circuit with a DC offset and the samples' raw values vary between |-244 , +244| when removed the DC offset . The key problem…
Just B
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