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For integer multiples, I can use a frequency divider after the VCO to get a multiple of the input frequency. But how do I multiply the input frequency by an irrational number, say \$\sqrt2\$?

In78
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  • Multiply by divider? – Eugene Sh. Nov 16 '15 at 21:05
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    You can approximate that number with a fractional PLL but it will be just that, an approximation. So you will have to decide how accurate you want it. In theory you could make any accuracy you want but there are disadvantages to that like low frequency spurious components popping up. – Bimpelrekkie Nov 16 '15 at 21:15
  • Building a synthesiser is different to writing a rational fraction. The fraction is noiseless, the synthesiser has noise, an irreducible phase noise. You can design a synthesiser that will keep the differences between its output, and theoretical, below the noise level. – Neil_UK Nov 16 '15 at 23:41

2 Answers2

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You can't.

You can get any rational multiple of the input frequency, because at intervals of some finite period the output and input will be exactly in phase with each other. With an irrational number, they can be in phase at exactly one point ever.

Why do you want this anyway?

pjc50
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  • Actually, this question was asked in an exam of my university... I guess the correct answer would be we can't – In78 Nov 16 '15 at 21:49
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    If they do suggest an alternative answer, I'd be interested to see it. – pjc50 Nov 16 '15 at 23:14
  • Are you absolutely sure there's no solution for /this particular/ irrational number. I suspect there is one due to properties of sqrt(2) as both a scaling number and the 45 degree triangle. I'd search LCR circuits of I needed one badly enough. – Joshua Nov 17 '15 at 03:40
  • Can this be done any other way without using a pll? To multiply a frequency by √2? – In78 Nov 17 '15 at 18:32
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Yes. You can build a synthesiser to generate a frequency of sqrt(2).

Can you write down an irrational number like sqrt(2), as a decimal fraction? Is it possible, even in principle? No.

But you can approximate an irrational number, as closely as you like, with a rational fraction. You can choose an error level, and write down a number that gets within that. For instance, using powers of 10 as the denominator as in the decimal system, to get within 1% error you could write 1.41. To get within 1 part per billion, you could write 1.414213562.

One problem with this is 'what is a suitable error level?' Computer users and developers have more or less agreed that 1 part in 2^56 using IEEE754 reals is more or less enough for most purposes. But for exact representation, only an infinite length will do. And that is not possible, even in principle.

However, a synthesiser is more than a rational fraction. It is a real piece of equipment, that exists in time and space. Very importantly, for our purposes, it has an irreducible phase noise in operation. The noise comes about from the physics of the components used. That means that for any given finite length of time operating, only a finite length of fraction is required to represent the output phase to an error can cannot be physically resolved.

So a synthesiser offers a solution to the 'how good should the approximation be?' question.

It is possible to build a synthesiser, whose output signal phase will be indistinguishable from that of an ideal theoretical signal source, not resolvable from the inherent noise of the synthesiser. That will hold true over any specifiable time, for instance a 1 minute measurement, my lifetime, your lifetime, the habitable lifetime of the sol-earth system, or any guess as to the lifetime of our universe.

This synthesiser would produce a signal whose phase advances by approximately sqrt(2) cycles per reference cycle, with a non-cummulative error. This is the functional definition of a synthesiser producing a frequency of sqrt(2)*ref.

An example fractional synthesiser would not, by itself, be able to produce the signal. As it has a fixed finite length denominator, the frequency it produced would have a finite error, which means the phase error would grow over time, would be cummulative.

A small modification to such a synthesiser however would use a computer to keep track of the phase error, and inject a carry into its LSB from time to time. Such hybrid synthesisers are in equipment in the marketplace. The delta phase for the LSB.update_period product would be small enough to be undetectable. Logically, this carry is merely an extension of the bitwidth of the denominator. Such a computer would be calculating the theoretical phase of the target sqrt(2) signal, perhaps by real time integration of a computable representation of sqrt(2) such as the infinite continued fraction [1; 2,2,2 ...]. This means that the long term phase error would be non-cummulative. The effective denominator of this computer would grow over time. Fortunately, the memory consumed in this process would grow only logarithmically with time, which means that the synthesiser could be implemented with present day hardware.

Perhaps a more fun ratio to synthesise would be the Golden Section, approximately 1.618034, [1; 1,1,1,1 ...] as a continued fraction, arguably the 'most irrational number'.

Neil_UK
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    If you use a rational approximation to sqrt(2) with any finite denominator, there will be an accumulating error from cycle to cycle. That error may be tiny, but it is not "non-cummulative". – The Photon Nov 16 '15 at 22:06
  • I was anticipating controlling the synthesiser from a [1;2,2,2,2,2 ...] infinite continued fraction representation of sqrt(2). With a sufficiently long fraction, you won't be able to tell the difference between that and sqrt(2) in the age of the universe. When you spot an observable deviation from theoretical, tap me on the shoulder. The meanest computer has enough RAM to implement a sufficiently long fraction. – Neil_UK Nov 16 '15 at 22:27
  • Nonetheless, whatever error there is, is an accumulating error. – The Photon Nov 16 '15 at 23:10
  • Non-accumulating! – Neil_UK Nov 16 '15 at 23:34
  • The error will accumulate over time! If you wanted a clock that was 2.1x faster, and you instead made it 2x faster, then every clock period the overall phase error would get larger and larger. Every so often the phase difference would drop back down, but in the mean time you would have lost a clock cycle. The same goes for if you need $\sqrt{2}$ and instead do a rational value close to it (like $577/408$ for example). In reality it depends on if synchronicity is required. If you need an asynchronous clock, close enough would likely do. (In fact $\sqrt{2}$ would by definition be async.) – Tom Carpenter Nov 16 '15 at 23:46
  • non-cummulative, edited answer to elaborate why not. I used to design 'difficult' synthesisers BTW. – Neil_UK Nov 17 '15 at 06:44
  • Would such a synthesizer still be considered a PLL? – Mast Nov 17 '15 at 08:53
  • @Mast that's the broader meaning of PLL as used in the OP, and this type of synthesiser would, or at least could, contain a PLL in the more restricted sense of just what you get in a 4046 IC. Obviously you have to wrap some dividers around a 4046 to make a synthesiser, and it's how those dividers are controlled that's the important bit. – Neil_UK Nov 17 '15 at 11:33