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enter image description here

The above give basic block diagram of PLL, but according to my understanding after the output of Charge pump with loop filter , VC ie the control source for the VCO is connected to which part of the circuit design of the basic VCO (based on cross coupled pair -negative resistance). The image for VCO is given in below. Does the control source for VCO connected to the current source at bottom in real life? enter image description here

Ps: I have added one more updated varac design. Is it like that

enter image description here

negative_feedback
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  • No, you need a much more sophisticated VCO than the one you show. – Andy aka Aug 22 '20 at 21:12
  • I have added one more image, will the output of loop filter connected to VC, or is it separate control source? – negative_feedback Aug 22 '20 at 21:22
  • Look up varactor controlled VCO. – Andy aka Aug 22 '20 at 21:33
  • the image which I have added in 3rd pic is varactor controlled vco, but my question was where will be the output of loop filter connected to VCO. will it be coneected to one of the input of varactor controlled vco or the bottom current source? – negative_feedback Aug 22 '20 at 21:45
  • are both Varicap anodes connected to Vc? Also the error frequency must be <<loop BW to capture. Plot or table response of each block and show all design specs !! – Tony Stewart EE75 Aug 23 '20 at 06:41

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Your third diagram shows a very good method of controlling a VCO's frequency with varactors.

The output of the loop filter would be connected to the common point of the two varactors.

Ideally, the reference for the PSD, and the ground point for capacitors in the loop filter, would be VDD, not ground, so using the same point as the reference for the varactor voltages in the VCO. This would minimise the tendency of any noise on the VDD line tending to modulate the frequency of the VCO. This can matter if you're trying to design a low phase noise system.

While the frequency of the VCO is not stable with respect to changes in the tail current, this is not the ideal way to try to control the frequency, as the effect is fairly weak, using the bias dependent parasitics of the FETs.

Neil_UK
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