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Questions tagged [xilinx]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

A popular manufacturer of FPGAs (Field Programmable Gate Arrays)—such as Spartan and Virtex—and CPLDs (Complex Programmable Logic Devices), including 9500XL and CoolRunner.

Xilinx homepage

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3.3V IC <-> 2.5V FPGA IO Bank

I want to connect a 3.3V TFP401 to a 2.5V spartan 6 LX45T FPGA. It looks like each device is tolerant to the other device's voltage: TFP401: DVDD Min: 3.0V Nom: 3.3V Max: 3.6V Input voltage range, logic/analog…
stanri
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Export RTL view and Waveforms as images from Xilinx ISE webpack

I think this is really a homework question, but moderators' call. I am trying to export the RTL view and waveforms of my verilog code into an image file (any format). But there doesn't seem any option to do that. What is the proper way to do this?
Rick_2047
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Spartan-6 FPGA Input voltage

We are using the Spartan-6 FPGA from Xilinx. VCCO banks of the FPGA are running at 1.8V. We a have MIPI IC that outputs serial data, but at 2.7V. Looking at the Specs for the FPGA, it seems to be able to handle up to 4V, at any Input. Spartan-6…
JakobJ
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Power Analysis in Xlinx ISE

I wanted to know the performance of the design in terms of switching activity (hence the power consumption) using Xlinx ISE. I have Xlinx ISE 14.3 webpack version. Is it possible to do such analysis? If so how do it? I'm novice in using Xlinx ISE,…
user40295
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What is the primary motivation behind combining A series and R series ARM onto an FPGA in MPSoC Xilinx devices?

The first entry into the SoC series from Xilinx was the Zynq SoC. It combined ARM cortex A9 processor with programmable logic to get the best of both worlds. The current generation contains Ultrascale+ devices that Zynq UltraScale+ MPSoC and Zynq…
quantum231
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Gate count and dynamic power calculation in Xilinx

How do I calculate the gate count and dynamic power for a design in Xilinx? I am doing a project on Xilinx using ISE 14.7. I do not understand the gate count and dynamic power for the design.
Kakali Saharia
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TX/RX pins on Xilinx Zynq

I have been using a Spartan 6 where the TX/RX pins are multiplexed with the IO pins, I can't find any dedicated TX/RX pins on the Xilinx Zynq Soc, is it a Xilinx thing to multiplex TX/RX with IO pins? I not able to find any thing in the data sheet.…
Alex
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what is the maximum frequency does the virtex 6 support

what maximum frequency does the Xilinx Virtex-6 support.How can i know that. As I was working with Xilinx, I want to know the range of frequency it supports.
subash
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