0

How do I calculate the gate count and dynamic power for a design in Xilinx? I am doing a project on Xilinx using ISE 14.7. I do not understand the gate count and dynamic power for the design.

Glenn W9IQ
  • 5,564
  • 11
  • 17
Kakali Saharia
  • 1
  • 1

1 Answers1

1

You can't get an ASIC-equivalent gate count directly on an FPGA. What you can get are lists of what FPGA primitives are used by the design. Check the _utilization_synth.rpt and _utilization_placed.rpt reports.

As for power consumtion estimates, check the _power_routed.rpt report. This will list the static and dynamic power, as well as temperature range estimates if you have properly specified the heat sink.

Edit: oops, you're using ISE. Primitive count will be in the .map, .mrp, and .par files. For power, you will need to run the power analyzer. See http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pp_p_process_xpower_analyzer.htm .

alex.forencich
  • 40,922
  • 1
  • 69
  • 109
  • Thank you.But how can I get the the exact power for the design? – Kakali Saharia Oct 11 '16 at 19:14
  • You need to run the power analyzer to get information about power consumption, ISE does not perform power calculations by default. – alex.forencich Oct 11 '16 at 19:16
  • I run it.But the main problem is there the dynamic power is showing zero mw.The ncd and pcf file were simulated.But vcd. file was not simulated.What would be the reason for it? – Kakali Saharia Oct 11 '16 at 19:24
  • @KakaliSaharia - Without knowing the exact inputs, there is no way to calculate the dynamic power. For static inputs there is no dynamic power. At the least, there are no clocks active. so no internal cells change voltage. – WhatRoughBeast Oct 11 '16 at 19:51