Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [asic]

An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.

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What are the practical uses of ASIC?

Microcontrollers, FPGAs, ASIC (Application-specific integrated circuit) all are used for similar type of applications (at different levels). I know about microcontrollers and FPGAs. But what is an ASIC really? I have a hard time understanding why we…
Codenamed SC
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Can you get a Passive ASIC?

In super small low power devices, where space is a big premium, complicated passive networks can take up a lot of space. Is it possible to get a passive or mostly passive ASIC fabricated? If it is possible, how much would it cost? Obviously it would…
BeB00
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What can go wrong when producing an ASIC from an FPGA-verified verilog design?

Given a Verilog design fully validated on an FPGA prototyping system, and someone who has never done an ASIC before, what are the chances that a service like CMP will ship fully usable chips on the first try? As far as I can tell, they provide the…
Tim
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ASIC Verfication Do I need to verify all possible combinations?

I'm currently doing ASIC Black box Verification. Suppose I got a module with 200 input ports with 12 bit width each and a one output port with 64 bit width. Lets say, its pure combinational inside. [11:0] …
e19293001
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ASIC Shuttle Service Disadvantages?

Im trying to learn a bit about the techniques to create an ASIC. I found that the NRE-Costs are the biggest cost part which means the creationg of the masks and you get a minimum number of ASICs back. Shuttle Services seems to be cheaper which means…
user30371
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When might a standard cell optimized for zero wireload capacitance be used?

Some standard cell libraries include cells optimized for zero wireload capacitance. When might these be used? Are these used when the output drives a gate that's physically very close to the output? I would have thought that even then, the driving…
Tim
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Can multi-project wafer service merge projects with different number of layers?

I would like to ask some help to better understand limitations of multi-project wafer services (MPW). In nutshell, i found about the service, that it merges many projects on wafer, so one project only have to pay for a share of its surface. While it…
cocox
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Why is static power more of a concern in smaller ASIC geometries than dynamic power?

I've read that the challenge of designing smaller ASIC geometry is the leakage current. I'm aware that dynamic power is the cause of most power consumption in CMOS, but leakage current is static power (I believe,) which must be extremely low in…
hontou_
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Designing ASIC Chip for Enterprise

I am new here and hope to glean some expert opinions. I am a disabled veteran and will be starting a bitcoin mining enterprise in the near future. I have done some research and feel that inquiring with some large asic makers to make a more…
Wellnavy
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65nm silicon-germanium

The Wikipedia page on silicon-germanium states that AMD and IBM worked on a 65nm SiGe process. Unfortunately the source is no longer up and I cannot find more information about the 65nm SiGe process. I know that TSMC provides access to 90nm SiGe…
Randomblue
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ASIC Hardware cost

Why is multiplication with a fixed coefficient cheaper in ASIC as compared to variable multiplication? Would it be faster using an FPGA inferring a DSP Slice?
Rahul Seth
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How to Implement Relational Operation using TCAM?

Can we implement relational operations (<, > , >=, <= ) using TCAM? Even if they are possible to implement, are TCAMs used for relational operations in real life? What are the pros and cons?
swr das
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ASIC v.s. State Machine - same difference?

Are ASIC chips the equivalent of "State Machines" in computer science ? There are no "programs" or "instructions" that are executed. All the changes occure because of the inputs on the gates when the clock changes state. Everything happens…
TechnoCaveman
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