Some standard cell libraries include cells optimized for zero wireload capacitance. When might these be used?
Are these used when the output drives a gate that's physically very close to the output? I would have thought that even then, the driving gate should be optimized for something higher than zero.
This is one of those nonsense areas you run across. Inside an IC there is very minmal inductance, so you end up with delays that are dominated by RC's and not RLC's. If you have RLC you get wave equation propagation and thus must deal with transmission lines and reflections etc. But the same PDE's (Partial Difference equations) when used with RC result in the diffusion equation and you don't get transmission lines (except in very rare cases with very long runs).
In fact pop by this page and look at the V4 driver which is "optimized" for zero wire load. The O/P drivers are identical to the the other minimal drive device, which indicates that there is no matching taking place. The only real difference is that they've reduced the P Widths in the logic cell so that the \$T_{rise} T_{fall}\$ is no longer matched.
The lower cell is the "optimized" one (snip taken from that link):
Having a cell like that might be useful, but not for the stated reasons. Capacitance is capacitance is capacitance wrt to how you drive it.
I would look into the cell and check out the transistor sizing's to make sure they haven't done something funky.
When the gates are physically close together, the wire load is very small compared to the loading of the gates themselves (the transistor gate capacitance). For practical purposes the wire load is zero.
Back in the past, the wire capacitance could be neglected as compared to gates' capacitance. However, today this is no longer true.
Now, when you say that the cell is optimized for zero wireload capacitance, I can think of two totally opposite optimizations:
The first option is bad. If you use cells that do not account for wires' RC delays you'll get optimistic synthesis timing. Once place and route will be completed you'll probably have many paths that do not meet timing. Depending on the post synthesis tools you have access to, these timing problems can be anywhere from "I don't give a s*** - the tool will do most of the work" to "f***, it'll take me a century to close timing". I'd avoid using these models at all, unless there is solid proof that this won't screw you up.
The second option is not that bad. If you assume that the synthesis will use a zero capacitance wireload model, you can compensate for this optimistic assumption by adding additional capacitance to cells themselves. I'd say that guessing that wires' capacitance will be equal to basic NAND2 capacitance is a good guess. If you indeed run synthesis tool with zero wireload model, this additional capacitances will prevent too optimistic netlist. If you run synthesis tool with non-zero wireload (with post P&R extracted values), the synthesis will not use these cells at all. However, I never heard of anyone who used this approach.
Zero wireload in general:
It is almost impossible to come up with a decent wireload model nowadays. Even custom models will give you just a rough estimation. The only way to close timing on today's designs is to extract the RC load post place and route. This fact led to a conception of "fast synthesis" - synthesize for the first time with wireload zero model, perform place and route, extract RC, feed the extracted RC back to synthesis tool and re-synthesize.
Sometimes during "fast synthesis" the uncertainty of the clock period is specified with higher value than required. This is the way to compensate for lack of interconnect delays.
However, I never heard that the cells themselves were changed in any way for the purpose of the above flow.
RC prediction during synthesis:
There were many attempts to come up with an algorithm to predict RC delays for each individual cell. I don't know how accurate these algorithms are. There is a high cost associated with these tools (for example: "Topological" Design Compiler by Synopsys is more expensive than usual DC; considerably more).
