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I've read that the challenge of designing smaller ASIC geometry is the leakage current. I'm aware that dynamic power is the cause of most power consumption in CMOS, but leakage current is static power (I believe,) which must be extremely low in CMOS. Why is static power more of a concern than dynamic power in smaller ASIC geometry?

JRE
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hontou_
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    leakage current ...... extremely low in CMOS It depends on the process. In many processes there is a choice: slow but low leakage / fast but higher leakage. So there is no "single truth", depending on what is needed, compromises are made. For an IC to be used in a watch (not a smartwatch), speed is no concern but leakage is. For a smartphone, speed and power consumption while in operation are the main issues. Leakage is less of an issue as the supply voltages can be lowered or even switched off. – Bimpelrekkie Nov 17 '21 at 10:36
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    the challenge of designing smaller ASIC geometry is the leakage current. Correct and that is not so much about the speed vs leakage but more about not letting the leakage currents get out of hand. It is harder to keep those leakage currents small when the rest of the transistor gets smaller. Also other effects that do not affect larger process nodes so much become more relevant like tunelling etc. – Bimpelrekkie Nov 17 '21 at 10:49
  • Define "smaller", what nanometre design? – Mitu Raj Nov 17 '21 at 11:34
  • Static power is typically small compared to dynamic power in contemporary CMOS nodes. Where did you read that static power is a bigger concern? An ultra low power design running at KHz clocks will certainly depend critically on leakage, but a 5 GHz PC much less so. Give us some context. – user1850479 Nov 17 '21 at 16:32

2 Answers2

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Lower voltage as discussed here...

The smaller feature size dictates lower supply voltages to prevent breakdown from excessive field strength; supply voltages below 1V are common..

The lower supply voltage dictates the voltage swing available for gate drive; with less than 1V swing, the gate threshold voltage must be kept low (OR alternatively, search for "sub-threshold operation" which was a buzzword a few years ago).

With the "0" input level so close to the threshold voltage, leakage current increases as the threshold voltage is lowered...

multiply this leakage current by the billions of shrunken transistors you can fit on such a device to get its static current.

This is just a sketch of the reasoning; hopefully someone with better knowledge of device physics can flesh it out some more.

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Six causes of leakage currents are listed here; Most books on micrometer and nano-meter CMOS have a more comprehensive treatment of the subject.

As transistor dimensions have shrunk into the micrometer and then the nanometer range, leakage current effects have become more pronounced. In other words, transitors don't turn off completely when they are supposed to and a small current (pA - nA range) keeps flowing through each transistor, depending on the process node. Leakage current is readily exacerbated by temperature. (Search: Bulk cmos leakage with temperature).

To counteract leakage currents, few techniques are:

  • backgate biasing has been in use for sometime now.

  • variants of the SOI bulk are used and there is extensive literature on it. A typical paper is linked here.

For a large chip, multiply this with billions of transistor on a chip such as a modern FPGA. This quickly becomes a concern and adds to power dissipation that in turn raises the temperature of the die as well.

For very small (wearable devices) it is still a concern as a small battery can supply so much in the first place but perhaps it is not that critical.

For CPUs in a laptop or desktop, this causes an inefficient component in the system and increases the heat-sink requirements, which puts an upper limit on how sleek a laptop may look.

For clouds/grids with 100,000+ CPUs, it reflects in the monthly bill.

For mobile devices, battery life becomes a concern as this phenomenon keeps draining the cellphone battery while the phone is turned on and is waiting for the next call.

Syed
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