Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [vhdl]

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) is a hardware description language used in electronic design automation to describe and design digital systems such as field-programmable gate arrays and integrated circuits.

VHDL is turned into logic through a process called synthesis.

Further reading

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VHDL: Converting from an INTEGER type to a STD_LOGIC_VECTOR

I built a mod-16 counter, and the output result is a INTEGER (all the examples I saw used INTEGER). I built a hex-to-7-segment-display decoder, and its input is a STD_LOGIC_VECTOR (wrote it that way because it was easy to map out the truth…
J. Polfer
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std_logic or std_ulogic?

It seems that the world has decided that std_logic (and std_logic_vector) are the default way of representing bits in VHDL. The alternative would be std_ulogic, which is not resolved. This surprises me because usually, you're not describing a bus,…
Philippe
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How to bring out internal signals of a lower module to a top module in VHDL?

How can I bring out the internal signals of my VHDL source code to my testbench so that I can view them as waveforms? I use Active HDL. I would like to know if there is any tool independent method of achieving my objective. Any help is appreciated. …
Suhasini
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How to divide 50MHz down to 2Hz in VHDL on Xilinx FPGA

I have a Xilinx FPGA board, with a 50MHz crystal. I need to divide that down to 2Hz in VHDL. How do I do this?
ABAYOMI STEPHEN
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When to use STD_LOGIC over BIT in VHDL

Whats the difference between using: ENTITY MyDemo is PORT(X: IN STD_LOGIC; F: OUT STD_LOGIC ); END MyDemo; and ENTITY MyDemo is PORT(X: IN BIT; F: OUT BIT ); END MyDemo; What are the limitations of using BIT over STD_LOGIC and…
Dean
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VHDL: OR-ing bits of a vector together

I want to OR the bits of a vector together. So say I have a vector called example(23 downto 0) and I want to OR all the bits into another vector, is there any way to do this that does not involve going example(0) or example(1) or ...example(23)?
biker of the apocalypse
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Do you use VHDL nowadays?

I'm an Electrical Engineering student and I'm studying the hardware description language known as VHDL. I searched for it on Google looking for an IDE (I'm on a mac), but this language seems pretty dead. So here is my question: in my future job as…
Francesco
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How to avoid latches during synthesis

I want to design a block of combinational logic using VHDL, but occasionally the synthesized result contains an unintentional latch. What coding guidelines do I need to follow in order to avoid the synthesizer from inferring latches? Example : in…
user5140
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What is the use of 'event in vhdl?

In vhdl code for synchronous counter, I replaced following part process(clock) begin if(clock'event and clock='1')then count <= count + 1; end if; end process with process(clock) begin if(clock='1')then count <= count +…
tollin jose
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Boolean in VHDL? When does '0/1' fail?

I was wondering as to why VHDL has a boolean data-type? When does '0' or '1' not cut it? Is boolean implemented differently?
Mikhail
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In VHDL, what is the difference between "downto" and "to"?

Are there differences between (x downto y) and (y to x)? Where should we use (x downto y)? Same question is for (y to x). Notation : x and y are integer
user5140
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Proper clock generation for VHDL testbenches

In many test benches I see the following pattern for clock generation: process begin clk <= '0'; wait for 10 NS; clk <= '1'; wait for 10 NS; end process; On other cases I see: clk <= not clk after 10 ns; The later is said to be…
Karsten Becker
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How do I link two components from different files in VHDL?

Sorry for the amount of code in advance (I added the code since I was unsure whether it is needed here to resolve my issue). My main goal is to link two components which are in two separate .vhd files together in a block in a third file. Lets say…
Clone
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Meaning of strong and weak drive in VHDL?

What is the meaning and effect of "strong" and "weak" drive shown by (0,1) and (L,H) in VHDL's package ieee.std_logic_1164?
manav.tix
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Set STD_LOGIC_VECTOR with constant integer

Is it possible to set a STD_LOGIC_VECTOR(6 DOWNTO 0) with a constant like so: signal s1: std_logic_vector(6 downto 0); s1 <= 12; Or do I have to define it as a set of bits?
Dean
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