verilog code with two falling edges

Question

Please look at the picture for this description. I have a problem with writing verilog for the following logic: Consider clk and R3 are input signals & out is the output signal. At the falling edge of clk, out is reset to 0. At the falling edge of R3, out is set to 1. How can I implement this logic in verilog? I am stuck because it seems to me that there is no way to distinguish between falling edge of R3 and falling edge of clk.

At the falling edge of both clk and R3, both clk and R3 are equal to 0 so I can't distinguish them.

    module startup(clk, R3, out); 
   input clk, R3; 
   output reg out; 
   always@(negedge clk, negedge R3) begin 


   end 
   endmodule

R3 and CLK are two different signals...of course you can distinguish between their falling edges. Show us the code that you have tried and explain why it didn't do what you expected. — Elliot Alderson, Apr 11 '19 at 14:28
@ElliotAlderson I have just added above. I don't know how to continue because I can't distinguish them. — emnha, Apr 11 '19 at 14:29
Possible duplicate of Verilog: Check for two negedges in always block — Elliot Alderson, Apr 11 '19 at 14:43
@ElliotAlderson could you apply it in my specific case? I don't quite understand the answer there. — emnha, Apr 11 '19 at 14:50
Your problem gets a lot simpler if you consider R3 as a low true reset signal instead of just a negative edge. The OUT will still clear when R3 goes low. This makes the Verilog code fit to the normal behavior of a single flop instead of a much more complex realization of the function — Michael Karas, Apr 11 '19 at 14:55
@MichaelKaras actually R3 can be high right from the rising edge of clk so that doesn't work. I should have said that. — emnha, Apr 11 '19 at 14:56
This can't be solved using synchronous (i.e., edge-triggered) techniques; it requires a true asynchronous state machine. — Dave Tweed, Apr 11 '19 at 15:00
@DaveTweed could you show how to do that with asynchronous state machine? — emnha, Apr 11 '19 at 15:01
Possible duplicate of Detection of simultaneous edges of two asynchronous clocks — dave_59, Apr 11 '19 at 15:02
Not right now. The design of ASMs is not trivial. Is there any chance that you could sample both input signals with a higher-speed clock and turn this into a synchronous problem? — Dave Tweed, Apr 11 '19 at 15:05
What's your target implementation technology? FPGAs are not well-suited to asynchronous design. — Dave Tweed, Apr 11 '19 at 15:20
Are R3 and CLK always non-overlapping pulses? Does the R3 pulse happen only once, like some kind of startup routine? — Kevin Kruse, Apr 11 '19 at 15:26
@DaveTweed I write it and then synthesis in Quartus and do logic circuits for my design — emnha, Apr 11 '19 at 15:35
@KevinKruse R3 can be always 1 or pulse that happens one time. — emnha, Apr 11 '19 at 15:37
Well, Quartus implies FPGAs (Intel/Altera, specifically). Perhaps you should give us a bit more of the "bigger picture" of what it is you're building. — Dave Tweed, Apr 11 '19 at 15:38
I am doing dc-dc converter and I need some logic control for that. It is a bit hard to do it manually so I was thinking about writing verilog, then synthesis it and see how Quartus generates the circuit. Once I get the circuit image from quatus, I can do it on my own from logic gate in PSIM — emnha, Apr 11 '19 at 15:41

Dave Tweed · Accepted Answer · 2019-04-11T17:18:16.630

Each input requires its own process. Create two "toggle" FFs, and then XOR their outputs together. Toggle the "set" FF when the output is zero, and toggle the "reset" FF when the output is one.

module dual_edge_ff (
  input set,
  input reset,
  output q
);
  reg set_ff;
  reg reset_ff;
  assign q = set_ff ^ reset_ff;

  always @(negedge set) if (!q) set_ff <= !set_ff;
  always @(negedge reset) if (q) reset_ff <= !reset_ff;
endmodule

If you're building this with discrete logic, you just need a 74xx73 (dual negative edge triggered JK FF) and a 74xx86 (quad XOR gate, use one section as an inverter).

score 1 · Answer 2 · answered Apr 11 '19 at 16:38

At the falling edge of clk, out is reset to 0. At the falling edge of R3, out is set to 1. How can I implement this logic in verilog?

First, you should consider whether your logic is realizable in the technology you're using. Since you are using Quartus, I'll assume you're targeting an FPGA or CPLD technology.

And the logic you're asking for is not a well known latch or flip-flop type, so you will not be able to implement it directly in an FPGA or CPLD.

A typical solution to this is to introduce a high-speed clock, maybe 10 or more times faster than any of your other signals, and use that to detect transitions in the original signals (code not tested)

module latch1 (input hsclk, 
               input clk, 
               input r3, 
               output out);
reg clka, r3a;

always @(posedge hsclk) begin
    clka <= clk;
    r3a <= r3;
end

always @(posedge hsclk) begin
    if (clka & ~clk) begin
         // Actions for falling edge of clk
         out <= 0;
    end
    if (r3a & ~r3) begin
         // Actions for falling edge of r3
         out <= 1;
    end
end

endmodule

Notice that if the falling edge of r3 and falling edge of clk occur within one cycle of hsclk of each other, then the r3 edge will take precedence. Choose the period of hsclk to minimize the risk of this happening.

Thanks for the help but I don't have a higher clock available. — emnha, Apr 11 '19 at 16:44
@anhnha, if your clk signal is actually a periodic clock, you could use the PLL in your FPGA to generate a high frequency clock from it. Otherwise, an FPGA is probably not a good solution to your problem. — The Photon, Apr 11 '19 at 16:50

verilog code with two falling edges

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