output is affected by the next clock period

Question

I am trying to write verilog code or or thinking about a circuit to do the function below. In the clock period n, if there is a falling edge on S1 then OUT is high for the next clock cycle (n+1), if no falling edge is detected then OUT is low for the next clock cycle (n+1).

Is this possible? Can anyone show me how to do this?

Answer 1

Use the solution given in verilog code with two falling edges, followed by another DFF. Adjust the edge directions as needed.

Putting it all together, you get:

module saw_falling_edge (
  input s1,
  input clock,
  output reg out
);
  reg set_ff;
  reg reset_ff;
  wire q = set_ff ^ reset_ff;

  always @(negedge s1) if (!q) set_ff <= !set_ff;
  always @(posedge clock) begin
    if (q) reset_ff <= !reset_ff;
    out <= q;
  end

endmodule

Answer 2

You don't want to have two different always blocks controlling one signal.

Here's my version to avoid that

always @(negedge s1 or posedge clk) begin
    if(clk)
        saw_a_falling_edge <= 1'b0;
    else
        saw_a_falling_edge <= 1'b1;
    end

always @(posedge clk) begin
    out <= saw_a_falling_edge;
end

This is inferring a DFF with asynchronous clear to drive saw_a_falling_edge. The clk signal is connected to the CLEAR input and the s1 signal is connected to the clock. The D input is tied high.

If you did it the other way around then if the clock edge happened while s1 was still low, the output wouldn't go high (violating the requested behavior per your timing diagram).

Be aware the above solution won't handle the case that s1 goes low while clk remains high. It's not clear to me from your problem statement whether you need to handle that or not.

Answer 3

In principle, you'd do something along the lines of:

input clk;
input s1;
output reg out;

reg saw_a_falling_edge;

always @(negedge s1)
    saw_a_falling_edge <= 1;

always @(posedge clk) begin
    out <= saw_a_falling_edge;
    saw_a_falling_edge <= 0;
end

In practice, this will probably fail timing analysis unless you can constrain s1 appropriately against clk.