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I'm recently learning qLDPC code. Although I've seen literature talking about the code construction, parity check, possible logical operation and decoding. How exactly do I prepare e.g. a logical phi state in the Hypergraph Product code? ... I remember when we deal with stabilizer codes we can prepare a logical 0 state using 0 initial states and measure the stabilizers, but how about arbitrary logical state? And are there any shortcuts for this?

Appreciate if you can attach the related paper! Thanks.

AndyLiuin
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2 Answers2

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Under noiseless conditions, you can create a encoding circuit, using Gottesman's algorithm for any $[[n,k,d]]$ stabilizer code. You can input any arbitrary $k$-qubit physical state, known or unknown, into this circuit and it will produce the corresponding logical state.


If you require fault-tolerance, then you can only prepare a known arbitrary state $|\psi\rangle_k$. By known state, I mean that you know a circuit $C$, such that $C$ acting on $|0^k\rangle_k$ creates $|\psi\rangle_k$. To do this, first create a logical zero state in a fault-tolerant fashion.

  1. Start with $|0^n\rangle_n$.
  2. Measure all the stabilizer generators.
  3. Use the outcome of these measurements to compare all subsequent syndrome measurements to.

With $|\bar 0\rangle_n$ in hand, use a fault-tolerant version of $C$ to create $|\bar\psi\rangle_n$.


Why can't you fault-tolerantly encode arbitrary unknown states? Well, suppose someone gives you a $|\psi\rangle_k$. And suppose you have some hypothetical fault-tolerant circuit [1] $C_F$ that will transform all such states to $|\bar\psi\rangle_n$. Well, think about the moment in time just before the first gate of $C_F$ is applied to $|\psi\rangle_k$. If an error occurs at this point, then there is nothing $C_F$ can do to identify the error, let alone correct it.

Technically, a fault-tolerant operation is one that restricts logical error probability to $\mathcal{O}(p^2)$, where $p$ is the physical error rate. An error that occurs just before the first gate in $C_F$ is a $\mathcal{O}(p)$ event, and it destroys the logical state with the same probability. Hence, the probability of logical error is $\mathcal{O}(p)$, and the circuit is not fault-tolerant.

[1] The hypothetical is that the circuit is fault-tolerant, not that it exists. We have already shown in the first paragraph that such circuits exist.

Abdullah Khalid
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General states is impossible; your gate set must be discrete to have fault tolerance. Even preparing simple states is hard. It's still an open research question. For example, Tomas Jochym O'Connor's talk at the QEC 2023 conference was on this topic.

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Craig Gidney
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