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If I'm using an IC in the 74HC or 74HCT family, and I'm not using all the input pins, I understand that I should not leave them unconnected because they will float. But what exactly should I do with them, and what are the pros and cons of the different options?

For example, if I'm using the 74HCT08, which has four AND gates, and I'm only using two of the gates, what should I do with the inputs of the other two gates?

I've seen various recommendations in various places, such as...

  • connect them directly to Vcc
  • connect them directly to GND
  • connect them to Vcc through a pull-up resistor
  • connect them to GND through a pull-down resistor

What are the pros and cons of each of these options? Which option is best for stability and low power consumption?

jnrbsn
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5 Answers5

23

There are a few considerations that have not been mentioned in other answers.

  1. Sometimes the unused input plays an important role in the logic of the part. An example would be a 4-input gate where only 3 inputs are actually used. In this case the logic level that you tie the unused input to must be selected properly or else the logic function of the used functions will not work.
  2. In some business / industrial segments it is necessary to test all functions in each part on the board even if they are not used. This is done to ensure that some nascent fault in a chip does not expose to a higher chance of catastrophic failure of the part. The addition of pull ups or pull downs on each unused pins allows automated test equipment to toggle the pins which would not be possible if they were hard tied to VDD or GND.
  3. There are cases where it is handy to keep unused gates available for possible future rework to tweak the design in the case of bugs found, need to invert or combine signals or other things. Pins hard tied to VDD and GND are very much harder to rework so added pull ups or pull downs provide access pads for the rework.
Michael Karas
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The default answer for CMOS inputs is to connect them directly to either ground or power. I would let routing dictate which. If it doesn't matter, connect them to ground.

I'd probably start out with them all connected to ground in the schematic, then maybe switch some to power during routing if it makes things easier. If you have a ground plane, then ground is the net that you can connect to while causing the least additional routing congestion.

In some cases, you can tie inputs to outputs. For example, tie all three pins of a AND gate together. It can end up in either one of two stable states, but you don't care which one. The advantage of that is possibly less routing congestion, especially if the three pins are next to each other.

Of course this trick of tying inputs to outputs doesn't work with gates that invert. Then you'd either make a oscillator or end up with the inputs floating at the absolute worst voltage for power dissipation.

Added

This has all been assuming these are inputs to totally unused gates, which is what I interpreted the question to be about. The polarity of unused inputs to used gates can certainly matter, and then you may not have a choice whether the input must be tied high or low. For example, if you are using only 3 inputs of a 4-input AND or NAND gate, then the unused forth input must be tied high for the gate to work as intended. Likewise, unused inputs to used OR or NOR gates must be tied low.

It is not necessary to tie CMOS inputs high or low thru resistors. This is not because CMOS inputs have series resistors built in, because they don't. It is because no high inrush current will flow nor any harm caused by holding a CMOS input at the power or ground level, even during power-up.

Olin Lathrop
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Connect to either Vcc or GND. It makes no difference. With no load on the outputs, the current in the internal transistors will be about the same.

Or use a pullup or pulldown - again it makes little difference, with the proviso that you'll use more parts than necessary, and if the resistor fails open, the floating inputs may cause baffling symptoms which will be all the harder to track down since there is "obviously" no need to check out the unused gates. I speak from experience when I say that an unused gate can produce mystifying symptoms on the output from a used gate in the same package.

Pullup/pulldown techniques are largely a hangover from earlier, pre-CMOS families.

WhatRoughBeast
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    Connecting unused inputs of an AND gate or an OR gate to either Vcc or GND does make a difference. The unused AND input to VCC and the unused OR input to GND. – Uwe Jul 13 '18 at 22:56
  • @Uwe - Do you have a source and a quantification on that? – WhatRoughBeast Jul 14 '18 at 03:14
  • I think @Uwe thought you were saying that it made no difference whether you tied an unused input to VCC or GND, when I think your intended meaning was that it made no difference whether you use a resistor instead of a direct connection. In case you didn't mean that, it wouldn't make sense to tie an unused OR input to VCC since it would make it always true, and tying an unused AND to GND would make it always false. Both of these situations sort of defeat the traditional application of a logic gate. – GuitarPicker Jul 14 '18 at 03:41
  • I think Uwe is talking about the unused inputs of a used gate which has more inputs than needed. In this case, an option could be to tie the unused inputs to a used input (of the same gate) – Razvan Socol Jul 14 '18 at 04:29
  • @GuitarPicker - Nope. The extremely high input impedance of CMOS is pretty much independent of input level (as long a it's at logic levels, of course). Likewise, with no output load my understanding is that the internal output current is essentially zero, since of the two parts of the totem-pole circuit one is non-conducting. The intermediate portions of the circuit may behave otherwise, of course, and that's why I asked for a source and quantification. Choice of input level makes a big difference for families like TTL, but my understanding is that this isn't true of CMOS. – WhatRoughBeast Jul 14 '18 at 11:20
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    If you connect an unused AND gate input to GND, the output of the AND gate will never go high, even if all used inputs are high. If an unused OR gate input is tied to VCC, the OR output will always be high, even if all used inputs are low. I do hope you will understand now and will need no source or quantification. – Uwe Jul 14 '18 at 12:02
  • @Uwe - True, but so what? Why do you believe that an unloaded CMOS gate will draw more current when its output is high than when it is low? It's not remotely obvious. And that is why I'd like you to back up your statement with a source. – WhatRoughBeast Jul 14 '18 at 12:35
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    I did not believe that an unloaded CMOS gate will draw more current when its output is high than when it is low. – Uwe Jul 14 '18 at 12:51
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    @Uwe - Then why do you think it matters if an unused AND gate's inputs are tied high or low? Why should an unused OR gate's inputs be tied differently than an AND's? You stated, "Connecting unused inputs of an AND gate or an OR gate to either Vcc or GND does make a difference." Why? Granted, the output signal level is different for the two cases, but why does that affect the OP's question? He asked about current drain, not unused signal levels. – WhatRoughBeast Jul 14 '18 at 20:27
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It doesn't really matter which of the options you choose, all will do what is needed in 99.99% of the cases. And in that 0.01% of the cases that this isn't true you will know and have good reason to do something different. I can't think of any examples where this would be the case though.

Using a resistor is pointless as CMOS logic inputs are very high-ohmic so there isn't going to flow any current anyway.

That leaves connecting to ground or supply as the only options, which one you choose doesn't matter, whatever is more convenient.

CMOS logic circuits only use current when they're changing states so that's why you should apply a fixed state at the inputs. Whether that's zero, one or a combination of both doesn't matter at all.

Bimpelrekkie
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    What do you mean by "a combination of both"? If you mean changing over time, that means it will burn some power as it changes state. If you mean floating somewhere between a solid 0 and a solid 1, then that's also an invitation to problems (can be pretty similar to leaving it unconnected). If you mean gate A is connected to power and gate B is connected to ground, then yeah, that's fine. – Jerry Coffin Jul 13 '18 at 22:53
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    With "a combination of both" that some pins are connected to ground and some other pins to supply. I did not mean changing the input of any pin because that would defeat the whole idea ogf keeping the input static. – Bimpelrekkie Jul 14 '18 at 09:47
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Direct answer:

  1. You are using a gate (AND, OR, XOR, etc), and only some inputs need to be used. Example: NAND gate with 3 inputs and you need only 2 inputs. In this case connect unused inputs to GND or VCC according to the logic result you want. Normally for NAND and AND, connect unused inputs to Vcc. For OR, NOR and XOR connect them to GND. If you don't do that: a) The logic resut will not be the expected one. b) The current inside the device increases. Hence, the so celebrated low consumption of the MOS family will not be verified and the device may be damaged, in the worst case.

  2. You are using a chip (AND, OR, XOR, etc) and only part of the gates of the chip need to be used. In this case connect all inputs of the not used gates of the chip to GND or Vcc. I suggest GND. THE OUTPUTS CAN BE LEFT NOT CONNECTED, according to Toshiba and Texas Instruments Guidelines I have read. If you don't do that: The current inside the device increases. Hence, the so celebrated low consumption of the MOS family will not be verified and the device may be damaged, in the worst case.

Note that these 2 situations above covers 99% of the cases. And no pull up or pull down resistors are needed. So, keep your design clean and simple.

Mauro Sousa
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  • Vote down because your answer covers no new ground over which other answers from nearly six years ago have already covered in detail. – Michael Karas Apr 04 '23 at 22:17
  • I disagree. I bring the new information that only the inputs must be connected to Vcc and GND. Outputs do not, according to literature from Toshiba and Texas Instruments, which facilitates the design of circuits and PCBs. This information is not said in the previous answers. Additionally I explain that the problem of floating inputs is to result in high current consumption, which can damage the circuits, an explanation that is not clear in the previous answers. – Mauro Sousa Apr 13 '23 at 11:54