VHDL signal assignments

Question

X: std_logic_vector(3 down to 0);
c : Std_logic;
d : bit;
s : std_logic_vector(1 down to 0);

In architecture

x <= c&d&s;

so is this signal assignment in Architecture is correct or wrong

IS bit and std_logic having same condition and is it possible to assign the same to std_logic_vector as in assignment?

This looks like homework so I'm not going to write an answer. It's incorrect, you need to convert at least one of the types. I have also edited the code to look nicer. In the future, remember to add four spaces on to the beginning of the parts that are code. — stanri, Feb 13 '18 at 11:56
Also have a look here: https://electronics.stackexchange.com/questions/51848/when-to-use-std-logic-over-bit-in-vhdl — Oldfart, Feb 13 '18 at 11:57
@stanri, indentation advice is subjective but since we're here: I recommend to OP use 2 spaces, not 4. Avoids wasting line width. — TonyM, Feb 13 '18 at 12:21
@TonyM the four spaces are defined by the markup. If you use two it doesn't put the code in a code block. See https://electronics.stackexchange.com/editing-help: "Indent four spaces to create an escaped
block" — stanri, Feb 13 '18 at 12:22
Sorry @stanri, read yours as what you thought OP should put in their VHDL source. Understand your point, you meant "that are code when posting on SE". — TonyM, Feb 13 '18 at 12:38
Type BIT defined in package std.standard and type std_ulogic (the base type of std_logic) defined in package ieee.std_logic_1164 are both scalar types - character enumerated types. There is no implicit type conversion for scalar types that are not numeric types. Package std_logic_1164 contains a conversion routine To_StdULogic to convert a value of type bit to a value of std_ulogic. — , Feb 13 '18 at 19:29

score 1 · Answer 1 · answered Feb 13 '18 at 13:20

1

VHDL is a strongly typed language. All vectors which you concatanate on the right side should be of same data type. And the data type of the result of the right side expression should match with the data type of the left side expression. In VHDL, "bit" is a 2-valued data type and "std_logic" is an 8-valued data type. They both are different.

answered Feb 13 '18 at 13:20

Mitu Raj

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std_logic is a resolved std_ulogic which is a character enumerated type having 9 values ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-') count 'em. Enumerated means the values are named, character means at least some names are character literals. The value is positional (which doesn't correspond between the two types). Those 'vectors' are single dimensional array types with an element type that is a character enumerated type. The concatenation operator is predefined for all single dimensional array types. – Feb 13 '18 at 19:35

VHDL signal assignments

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