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I'm in the R&D stages of a V4 of my project, which may replace the high-speed DSP with an FPGA.

I was looking at this FPGA, because it is cheap: XC3S50A (about £6.50/each.) I think I can probably fit the project onto there, with one concern. I can't find anywhere in the datasheet about how much current it will consume. Is it a fixed amount, or does it vary, depending on how much logic I am using? Is there a quiescent current draw by it, when no logic is in use? What about the current draw by its clocks/PLLs? I've looked through the datasheet - it has many characteristics, but these ones in particular don't seem to be mentioned.

Thomas O
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    Would suggest you try writing the HDL in simulation, and then buy and test it on an eval board (even if a bigger chip in the same family), before committing to a PCB. The latest generation FPGAs will probably be lowest power, but will also require low core logic voltage supplies. – Chris Stratton Jan 03 '11 at 01:09
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    Yeah - buying an eval board isn't an option at the moment due to my low R&D budget of about £0. – Thomas O Jan 03 '11 at 02:50
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    Make friends with your local distributor sales reps, many times you can get a loan or free sample of a part or eval board off of them - especially if the hardware has been around a while. – Digikata Jan 14 '11 at 17:47
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    @digikata - It's hard to make friends with your distributor sales reps when your R&D budget is one of $0 or £0. – Kevin Vermeer Jan 14 '11 at 21:45

5 Answers5

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It varies hugely with clock rate, exactly what is being clocked internally, and I/O usage. It is sufficiently hard to determine that most FPGA softare has a utility to estimate current draw of a design given the external clock/data rates, however it will need a lot of detailed info to give a reliable estimate, so the easiest option is often to just build it & measure, or load a comparable design into a devboard and measure that.

mikeselectricstuff
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    The Altera and Xilinx software will estimate your power consumption, but you need to enter in your full design, clock frequencies, the I/O loads, and example waveforms. – W5VO Dec 31 '10 at 16:02
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    If you have a choice, you can usually reduce the power consumption of a given device by reducing operating voltage and slowing down clock frequencies. – vicatcu Dec 31 '10 at 17:24
  • What @vicatcu suggests is supported in very few device families. – Brian Carlton Jan 01 '11 at 02:54
  • Well, generally the FPGA core voltage will be set at something pretty low to begin with, such as 1.2V. You can't really mess with that too much. You can, however, change your I/O voltages, which can get you some savings. Also, your clock frequency is whatever you want it to be. Slowing the clock down can show significant power savings. – W5VO Jan 02 '11 at 13:10
  • I'd strongly recommend against deviating from the nominal core voltage specified for the device; it's playing with fire. The FPGA vendors guarantee that the device will operate at that voltage (+/- 5--10%). The tolerances/fluctuations of your power supply, and variability of the FPGA's characteristics, will lead to failures over large amounts of manufactured systems if you're operating at or close to the absolute min or max. – Saar Drimer Jan 14 '11 at 16:35
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There are two main "types" of power consumption:

Static: the power consumed while the device is on but doing nothing. The proportion of static power in the total power generally increases as technology dimensions shrink. In 90 nm and below it is a significant portion that must be factored into the power budget.

Dynamic: the power consumed while the gates inside of the device (including I/Os) change state (i.e., got from 0 to 1 or 1 to 0). That's why the operating frequency and functionality increases the accuracy of the estimate.

Xilinx has two tools for estimating power:

  • An excel sheet, as pointed by Brian Carlton.
  • A binary called 'xpwr' (part of ISE) that takes your placed-and-routed design (.ncd) and tries to estimate the power based on actual (well, predicted) use.

Obviously, the second method will be more accurate, but you could get a ballpark for your power budget with the excel sheet before you have a complete design if you need to design your board.

Of course, the best method is to complete your design, run it on a prototyping board, and then measure the consumption. That rarely happens in practice, though, because the FPGA design and board bring-up usually happen in parallel.

(BTW, we're trying to start an SE site dedicated to FPGAs... consider supporting it... http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fpga-design?referrer=YmxhQ2OJUo-FAaI1gMp5oQ2)

Saar Drimer
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  • A question: XPWR got an -tb swith (ISE8.2) for time-based power estimation which provide power trace vs. time, however it is not available now. do you know any equivalent for that? – VSB May 04 '15 at 11:40
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For that part the answer is here. For other parts, Xilinx has this page

vicatcu
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Brian Carlton
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Looking at power use, there are two primary differences in FPGA types.

First, there's the SRAM-based families from the leading vendors like Xilinx & Altera. They draw a lot of static power. Too much, I think, to be useful for anything that's really "low power". When these two companies say low power, they mean lower power than before (or than the other big guy).

The second class is non-volatile. There's a few people with these, but Actel's probably the biggest company that I've actually seen in people's products. They generally use orders of magnitude less static power. They tend to be slower devices. They're also highly resistant to IP theft.

I just went through this looking for an FPGA for a low power industrial temperature grade system I'm working on... I want to use Actel but I can't convince myself I'd be able to actually get the I-suffix parts when I needed them. I still haven't really solved this problem. I'll probably just try to squeeze the design into CPLDs.

darron
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It's true that the power estimation tools made by the vendors are the best tool to get information.

However, to get a feelinig, A "full" Altera Cyclone 3 I have recently encountered uses something like 0.8 A on the 1.2 V rail and not much (1...50 mA) on its 3.3 V and 2.5 V rails. It totals to a bit more than 1 W when running.

Since the 3.3 V rail is pretty much just used for the IOs, the FPGA will draw whatever the connected circuitry requires from this supply rail.

zebonaut
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