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I have a Lynxmotion hexapod which uses hobby servos for each of its 18 degrees of freedom (DOF).

The basic problem with this is that I cannot get data on the joint angles. I have modified the servos so that I can measure their orientation via the signal from the pot. For each DOF I want to read in the orientation of the servo via ADC and use a PID controller to generate the appropriate PWM signal. This works simply enough with an Arduino for one servo.

Unfortunately I have not found any microcontrollers with 18 10 bit (or higher) timers capable of generating PWM and 18 ADC. As such I am exploring the idea of using an FPGA. Specifically I'm considering the Papilio Pro FPGA. In reading about it I see that it has around 500,000 logic elements. While I'm new to FPGA I'm guessing this is the most crucial metric for my needs (if I'm wrong, please feel free to correct me).

The question in my mind is, how many logic elements do I need for my application? Are there any good rules of thumb for such calculations?

Chetan Bhargava
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DaemonMaker
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    Why do you need such high-resolution feedback of the position of all joints? If you're trying to do such precise movements, the real problem here is the fact that you're using hobby-servos at all. Furthermore, most hobby servos have something approximating a PID loop in their internal controller already. – Connor Wolf Jul 08 '13 at 08:11
  • If you're dead-set on hobby servos, maybe you should look into the OpenServo project. It's a open-source controller board that replaces the normal controller in a standard servo. It then provides a I2C control interface, so you get bi-directional comms, and can query it's position, tweak it's PID loop, etc... – Connor Wolf Jul 08 '13 at 08:19
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    You should be able to generate those 18 PWM channels in software on a single µC, if it still has some cycles (and 18 IO pins) to spare. – JimmyB Jul 08 '13 at 12:45
  • Looking more closely @ConnorWolf I would say 8 bit ADCs would be fine.

    I have looked at the OpenServo project. In fact I have a SparkFun OpenServo. Unfortunately it doesn't fit into the servos and I can't find size specs for the v3.

     – DaemonMaker Jul 08 '13 at 15:20

3 Answers3

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For several years, FPGA vendors haven't really advertised "equivalent logic gates", because it's a very poor metric for how much functionality can be achieved in a given FPGA.

To get a more complete picture of what's available in the Papilio, you want to look at this table from the Spartan 6 Family Overview:

enter image description here

According to the Sparkfun page you linked, the device on the Papilio is the XC6SLX9, the second row in the table.

In a system like you're describing, the limiting resources are likely to be the flip-flops. It's fairly straight forward, once you start thinking about your design in detail, to work out how many flip-flops are required. Given 11,000 flip-flops, you should easily be able to manage 18 counters and control logic.

Another resource to look out for is I/O. With 18 10-bit ADC's you'll probably either need to use a serial interface to connect to them, or a multiplexed parallel interface. You'll also want to make sure that the Papilio board pins out enough of the I/O pins, and that they accessible I/O's can be selected to the voltage levels you need (which may require digging in to the Papilio documentation or the datasheet for the specific S6 device you're using).

If you were designing a microcontroller or doing DSP-type functions, the block RAM or DSP slices could be the limiting resource, but I doubt you'll have problems with those in your project.

The Photon
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I think it's not possible or not the best way to try to figure it out by hand. I'm thinking about designs using thousands of elements written in HDL where the direct relation to gates and logic cells is not obvious. In addition, most FPGA ICs grow by doubling its size from one model to the next one, so it does not make much sense to know exactly how much silicon you need, just an order of magnitude is fine. My advice is you try with Xilinx ISE or Altera Quartus, write a first approach to your code and try to fit it into a device beginning with the smallest ones. You'll easily find the right one. You should be using between 50% (otherwise you'd better get the smaller one) and 80%. Don't try to squeeze things up to the point of using 90+ % of it, as all designs change don't they? and you'll get into trouble if you find out a bug and need some extra hw there then it does not fit into your "optimized" device. Be a bit generous, that's why exact reckoning of resources is rarely used or not at all.

Joan
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What you are asking for is not easy to answer.

If you need 18 timers, you can either create a timer and instantiate it 16 times, or you can create a state machine that handles 16 different counters. It al depends on how much time you want to spend on the design and what is your desired frequency. For motor control, I bet you can create a pretty simple state machine with 18 counter registers that is very very small. Creating PWM is even easier, what you need is one free running counter and a logic that compares the range of the counter and creates your signal, then you instantiate that 18 times. The whole logic will be less than 1000 flip flops.

And for the ADC, how are you planning to connect 18 ADCs to the FPGA? Because that can be the tricky issue here.

FarhadA
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  • I am only learning about FPGAs. I was under the impression that I could designate the pins as ADC pins. But then I may using the wrong terminology here. – DaemonMaker Jul 08 '13 at 23:45
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    Well both yes and no. FPGA is digital, there are some modern FPGAs like Xilinx Virtex 7 devices that have integrated ADCs but they are very expensive (you can get a Zynq board which has an ADC connector on it as well, but that is around $300).Since you need 18 ADCs, I would rather go for a multi-channel 10 bits LCD. Maxim has ADCs with 16 channels, but there are plenty of 8 channel devices out there. – FarhadA Jul 09 '13 at 08:49
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    sorry, i meant 10bits ADC :) – FarhadA Jul 09 '13 at 15:49