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From: https://fscdn.rohm.com/en/products/databook/applinote/ic/power/switching_regulator/buck_converter_efficiency_app-e.pdf

Can someone explain why the high-side MOSFET causes a loss due to its C_OSS. The charge from the C_OSS flows to the load, so why is it considered a loss?

In a sense, the C_OSS charge from the high-side does not flow to ground, it flows to the output, so it is useful charge being supplied to the load.

Tim Williams
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muosac
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2 Answers2

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Can someone explain why the high-side MOSFET causes a loss due to its C_OSS. The charge from the C_OSS flows to the load, so why is it considered a loss?

Consider firstly a resistor passing current; it's the same current going in as coming out hence the charge rate is the same but, a resistor takes energy from the flow of charge and, converts it to heat (gone!). A capacitor doesn't produce heat but stores the energy extracted from the flow of charge as a terminal voltage.

So, when the upper MOSFET turns on (activates) it shorts out that capacitor and dissipates the stored energy as heat.

Andy aka
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  • In that case, the loss equation should include the resistance or the load current. The equation they have given is independent of both. – muosac Dec 04 '23 at 18:18
  • @muosac The energy dissipated is the energy stored in the capacitor, regardless of the resistance it's discharged through. This is sometimes given in datasheets as E_oss. – Tim Williams Dec 04 '23 at 18:25
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    Ohh, I get it now. Your use of the word 'short' cleared it up. The C_OSS of the high-side is fully discharged through the on-resistance of the high-side. So there is a small loop formed with HS channel resistance and C_OSS of high-side. – muosac Dec 04 '23 at 18:56
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Assuming IL is positive when you turn your high side switch on (Minimum inductor current >0), VSW will start at about -0.7V due to low side diode conduction during the dead time.

Because of this, the current you put into VSW will initially have a return path through ground, since it has to conduct at least ILmin amount of current before the low side diode can turn on and allow VSW to start slewing high.

Edit: Think of Coss as a capacitor between VSW and IN. Right before you turn on your high side switch, this capacitor has V(IN) plus a diode across it. When you turn on your high side switch, you are discharging this capacitor. The current loop is local; it's just from the top of the capacitor, through the switch, then back into the bottom of the capacitor. This does not go to OUT.

mapplejacks
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    Note that this is true independent of the mechanism, i.e. whether diode reverse recovery, delayed low-side turn-off (shoot through), or plain old capacitance (Coss at Vds ~ 0 is generally extremely large compared to what Coss(Vds(max)) is). The mechanism changes the exact waveform, or over what voltages the bulk of the current flows at, but the overall effect (some turn-on "hard switching" loss has been incurred) remains. – Tim Williams Dec 04 '23 at 18:29
  • But, the current put into V_SW will go towards the load, hence LESS of the load current will flow via the low-side body diode freewheeling path. That will keep happening until the high-side can fully sustain the load current without needing the free-wheeling path. – muosac Dec 04 '23 at 18:32
  • @TimWilliams the exception to this is if you have enough negative minimum inductor current (e.g. forced CCM at light load) that VSW slews high via the inductor within your dead time. – mapplejacks Dec 04 '23 at 18:47
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    Yup; you assumed forward CCM so I was going off that. And to round that out: somewhat of a hybrid case exists for ZCS, i.e. in DCM (sync rectifier mode), with turn-on either during switch node ringing (can get partial or full ZVS depending on condition + using a valley switching control), or switch node stabilizes to mid-supply thus not incurring full Eoss loss. – Tim Williams Dec 04 '23 at 19:09
  • @muosac There are three paths on the SW node: high side, low side, and inductor. The inductor limits dI/dt along that branch, so switching-edge (commutation) events can generally ignore that path; put another way, we can simplify the circuit at short time scales, approximating the inductor as a current sink. – Tim Williams Dec 04 '23 at 19:12
  • @muosac I edited my post to answer your question as to why the current from the extra capacitance does not go to OUT – mapplejacks Dec 04 '23 at 19:18
  • @TimWilliams Sorry, I didn't mean to contradict you; what you said is true for the assumptions I stated. Sounds like other the case you're describing is something like quasi-resonant architecture, which is something I'm currently exploring in design. For light load (skip mode) DCM, VSW will settle to OUT, so that specific loss term should get better with more extreme buck ratios. – mapplejacks Dec 04 '23 at 19:24
  • No worries; I've been viewing this comment chain as an expansion of ideas or conditions, and these are all good points. And, feel free to incorporate these comments into your answer if you like :) – Tim Williams Dec 04 '23 at 19:29