I'm trying to make a slave device that gets power from a bus - per spec, I am allowed to draw 24 V, 6 mA maximum (the bus goes to 36 V sometimes, and under certain circumstances I'd be allowed to draw more power - but not always, but we can assume the maximum allowed current to be drawn is 6 mA).
I have yet to do test measurements on the bus, and I can't find good documentation on how the bus handles short bursts of high current consumption; I assume this would also differ from the implementation on the device that implements the bus. What I do know is that sending data from the slave to the master is done by modulating the power drawn up to 11-20 mA.
I do not need to send any data from the slave to the master; I am only reading periodically pushed data, so I do not need to modulate the bus current; but going above 6 mA might stop transmission from the master.
How can I limit the current my device may draw without affecting efficiency (or keeping efficiency above, let's say, around ~95%)?
I can take ample time to charge a capacitor (or multiple) to act as a buffer for the switching; even with an impact on effiency as long as it is during the 'setup' process, not the 'running' process. Simply using a circuit such as implemented in for example a PSSI2021SAY already uses up ~30 mW steady state in my preliminary LTspice simulation limiting the current to ~6 mA, which, compounded by the efficiency of the SMPS would leave me below the power required for my circuit.
