In my current environment, the interrupt source comes from an FPGA on a daughter board and connects to a GPIO pin on an EVB:
daughter board (interrupt output signal from SD controller)--> EVB(GPIO pin with interrupt enabled).
The GPIO interrupt polarity is set as active-low. The GPIO pin's voltage is 3.3 V and the daughter board output signal is 0 V.
When I connect both signals, no interrupt is triggered.
If I connect the ground pin on the EVB to the GPIO pin, an interrupt can be triggered.
It seems that the daughter board output is not 'strong' enough to drive the GPIO pin to low.
I am not familiar with the details of electronics wrt GPIO interrupt level-sensitive trigger mechanism.
How is this possible?
What is a possible solution for it?
Update: Problem Now Solved
I have since resolved the issue.
The reason is that on the daughter board there is a switch (with a indicating LED) to turn on the pins. I was not aware of this switch until I report the issue to the FPGA engineer.
 
     
    