Doubt regarding SR latch

Question

I am having trouble visualizing an SR latch intuitively. Here the two outputs \$Q, Q'\$ both are dependent on each other,so how will the two function at the same time?

Let me break it down. Suppose I am just creating the circuit. I take one line of \$S\$ and connect it to a NAND gate, then take another line of \$R\$ and connect it to another NAND gate. But then I connect the output of first gate to the input of second gate and vice versa. How are the outputs even defined?

Suppose, just after making the circuit, I want to know the value of \$Q\$; it is dependent on \$Q'\$. Then I want to find the value of \$Q'\$, and now it is dependent on \$Q\$ again. This is kind of contradictory to me.

Answer 1

You're getting misled by the very simple Boolean logic model of the actual complicated digital logic circuit and power supply operating at a temperature.

Digital logic is just 'convenient analogue'. Remember to never lose sight of the actual analogue circuits in that logic. Each of the logic gates is a very high gain amplifier and the SR latch has high-gain positive feedback. The input thresholds are not balanced and the circuit has an indeterminate region. Individual gate transistors can have a relatively wide tolerance.

The Boolean arithmetic model of the circuit has none of this. It's just an expression. The model is just that: an approximation of the electronic circuit's behaviour. It's a very valuable tool if applied to the circuit within the strict confines that digital logic is to operate in: good supply voltage, sharp rise/fall times, light output loads etc.

The real circuit has quite a different situation. On power-up, which the simple SR latch model doesn't accommodate, the power will rise to VDD. While it's below its minimum range, the slight difference in each gate's behaviour will cause the SR circuit to tend towards one stable state or the other. It's unlikely to power up into metastability unless the supply has a very fast rise time.

To model this actual behaviour would need very accurate and unavailable data about the characteristics of each gate transistor in each bought IC, as well as the operating characteristics of each board: supply voltage noise and temperature.

Without that, the power-up state must be considered random. It's most probably not, as the part characteristics and tolerances probably have a greater bearing than the supply noise. But its the most reliable simple view to take, especially when looking at large numbers of the same circuit, such as in mass production.

Answer 2

After powering up, the initial state of the latch is random. Just pick one of the gates, pick its output state (low or high), and then derive then other gate's state. For all four possible choices, the output states will be consistent.

In practice, you have to initialize the latch by pulling either /S or /R low. (When either input is low, the latch goes into a defined state regardless of what old state was.)

Answer 3

The Rules for RS latches are simple.

• You must force an initial condition with some power-on bias circuit.

• When both input states are active low, then both output states are active high.

• The first to release the input active state determines the other output state is latched. sim

misc. irrelevant info.

Coincidentally, this is also how N-key rollover keyboards operate after N=2 is depressed. More keys may be pressed but key presses are not displayed or latched in memory until they are released. This often causes typing errors when letters get reversed as a rapid succession of keys depressed gets the 3rd letter reversed when releases before the previous entry.

Answer 4

An R-S latch is one example of a bistable circuit. All bistable circuits share one thing in common: positive feedback to reinforce the current state. That provides the ‘sticking’ action to make it stay there once it’s set.

When a bistable like an R-S latch powers up, its feedback isn’t known, and its output state is not defined. It could power up and settle into of its two states, or possibly hang up in a third state called metastable.

More about metastability here: http://www.asic-world.com/tidbits/metastablity.html

What usually happens however is that there is a circuit bias toward powering up in one state. Even without such a bias, random events like power noise can push the latch out of metastable and to one state or another.

Regardless, you cannot count on the latch state at power on. Good design practice using R-S latches (or any kind of sequential logic for that matter) needs to provide a means to ignore their state until they can be initialized.

Answer 5

Suppose, just after making the circuit, I want to know the value of Q; it is dependent on Q′. Then I want to find the value of Q′, and now it is dependent on Q again.

The way I see it, your question is about "how do I find the initial boolean state of this circuit, given that initial state of each output depends on initial state of the other output which is yet unknown".

Start with considering the value of Q and Q' right before powering the circuit up. At that moment both of them are definite: 0, both logical value and voltage. No contradiction thus far.

Then, as you apply power, the NAND gates (both of them) start inverting those zeros, moving them towards logical 1. But that transition can't be instant; nothing is. And as long as those two gates aren't absolutely identical down to the atom -- one of them might have slightly longer trace, or a slightly greater transistor gate capacity -- one of them would eventually win: its output will leave logical 0 zone faster than the other gate triggers, thus canceling the other gate trip and thus bringing the entire circuit to some stable state.

Exactly which state that would be -- that's anyone's guess. Even the slightest EM noise or a temperature gradient may play a role. That's why we say that the initial state is random, we simply cannot account for all conditions that may affect it.

Answer 6

You're overthinking this. The R/S circuit at powerup is like a pencil balanced on its point. That's not stable, and the pencil will fall. But will it fall to the left or the right? If you carefully balance it, there's no predicting.

We analyze these circuits using logic, but traditional logic struggles with self-reference, which is what we have here. On the other hand, physical systems have no special difficulty with self-reference.