Which bus protocol(s) does a motherboard use to connect to RAM?

Question

I'm trying to learn about the protocols busses use in computer engineering and so far I've learned about the CAN bus protocol, where you can even watch traffic on the busses with wireshark, but this is typically used in cars and some micro-chips. Next I want to learn about the equivalent to that protocol for busses on a computer, specifically the one connected to RAM if there are multiple. What's the protocol or "type" of bus called? If there are many different bus types used on different motherboard architectures, I would also like to know a basic list of which different bus types are used, or at least what terms or manuals I can use to find out.

Answer 1

Some form of DRAM protocol is used. These are defined and maintained by the members of an industry organization called JEDEC, and a number of versions have evolved over time to keep pace with increasing performance.

Common ones in use for DRAM now include:

• DDR3, DDR4 for desktop main memory
• LPDDR3/4 for mobile / laptop
• GDDR5 for graphics
• Hyperbus or Xccela for embedded systems

Generally, the DDRx type use separate address / data buses, and use a pin-reduced row+column address scheme. Besides the protocol, JEDEC also defines form factors and pinouts for both individual chips and multi chip modules like DIMMs.

What does ‘DDR’ mean, besides an arcade game? It stands for Double Data Rate, which means that data are transferred on both clock edges. DDR is a synchronous (clocked) DRAM, so it’s called, in full, a DDRx SDRAM (x being the generation.)

This distinguishes DDR from earlier, single-data rate (SDR) SDRAM protocols, and from even earlier asynchronous DRAMs which had no clock, only control signals.

Hyperbus/Xccela are relatively new, targeting embedded systems and vertical markets like automotive. They share address and data on the same pins. Both are descendants of 8-bit SPI, and like DDR also use a double-edge clock to increase throughput. Hyperbus is a JEDEC standard, Xccela is not, although it leads in market share. They are very similar, but not 100% compatible.

There are serial DRAM bus schemes that use high-speed serial/deserializer (SERDES) connections instead of parallel data. One such scheme, called Hybrid Memory Cube, (HMC) combines stacked DRAM die with SERDES links to achieve both high density and throughput. So far it hasn’t gained market traction compared to a competing non-SERDES stacked-die technology called High Bandwidth Memory (HBM), but work continues given renewed interest in HMC in for bandwidth-intensive applications like AI. More here: https://www.eetimes.com/hbm-flourishes-but-hmc-lives/

Nonvolatile memories use these main interfaces now:

• SPI for low-level NOR boot code
• eMMC for bulk NAND flash
• PCIe (NVM Express) or SATA for larger arrays like M.2 cards

Answer 2

As mentioned in hacktastical's answer and SteveSh's comment, due to the very tight performance requirements for RAM, the interfaces typically are not specified using the neatly layered protocol stacks with clearly defined interfaces between the independent layers that you may be used to from networking protocols. Instead, they often smash together everything from the electrical interface, and sometimes even the physical connectors, over the timing and signals, up to the bus protocols and sometimes even the programming interface into a single interface specification.

So, there is no real distinction between the definition of "GDDR5 SDRAM" and "the bus protocol used to connect GDDR5 SDRAM memory to GDDR5 SDRAM memory controllers". And this applies pretty much to every {G}DDRx DRAM, ever.

Note also that for the same performance reasons, the memory controller is nowadays often integrated into the CPU. In fact, sometimes even the memory is integrated at least into the same package. So, it's not necessarily the motherboard connecting to the RAM, but the CPU directly, and the RAM may not even be on a physically separate location on the motherboard from the CPU.

One set of memory interfaces that was not yet mentioned, is High Bandwidth Memory (HBM), currently available in versions 1, 2, 2E, and 3. As the name implies, HBM targets systems which require high memory bandwidth, e.g. network processors (NPUs), GPUs and GPGPUs, and AI accelerators (for all three of those also for implementations as ASICs and FPGAs), as well as gaming consoles, and general-purpose supercomputers.