Dangers of analog levels on digital PIC inputs?

Question

I'm intending to use a PIC16F675, because it's what I have laying around, for a very simple task that involves turning on or off LEDs in response to changes in a pair of photodiodes. It really could all be done with basic components, but I'd much rather spend my time writing Assembly than tuning transistors.

At any rate, the 16F675 does have an ADC, but I don't want to use that, because I want the chip to sleep and respond to "digital" interrupts instead. This would normally be pretty straightforward, just drop in a potentiometer and turn it until the chip sees a "high" value when the correct amount of light is hitting the photodiode.

However, the datasheet has a warning I've never seen before:

Analog levels on any pin that is defined as a digital input, may cause the input buffer to consume more current than is specified.

This raises a few questions, most notably, what does this actually mean, and also why? According to the specs, 3V is well within its logic high range, but is this going to damage the chip by causing too much current draw? Or is it actually just a warning that the overall power consumption may go up compared to what the datasheet indicates? What if I instead wanted to connect a 3.3V digital output from another chip to it, would the same issue apply?

Answer 1

The input buffers on a microcontroller are complex circuits as they need to serve several purposes like input, output, analog I/O, built in pull up resistor etc.

However, when used as an input it can be seen as a standard CMOS inverter:

^{simulate this circuit – Schematic created using CircuitLab}

As long as we apply a voltage at input that is low enough (like 0.5 V or less) then this input voltage is treated as a "0", the PMOS will be on and the NMOS will bo off. So no current flows (the "to MCU internal circuits" has a high impedance input, no current can flow into it) and all is well.

When we apply a voltage at input that is high enough (like between Vdd and Vdd -0.5 V) then this input voltage is treated as a "1", the NMOS will be on but the PMOS will be off. Again, no current flows.

However we would apply a voltage that is close to Vdd/2 then both the NMOS and the PMOS will conduct. Then a "cross current" will flow from Vdd to ground. This is the current that the datasheet is talking about.

If you do this on only one input the current will not be a problem (the MCU can handle that, it wil not be damaged) but the current will flow and that will drain your battery.

So you can do what you propose but it is not a power efficient solution and depending on the voltage at the input, your battery might drain faster than expected.

Possible solutions:

Use a low-power comparator to do the voltage level detecting, a comparator will also consume some current but you know how much that is going to be (see its datasheet) so you can check if that current is low enough. Then the comparator's output goes directly to the MCU's input.

If you can live with a small time delay, use "polling" instead of an interrupt. If programmed correctly an MCU can wake up every second and check the input and go back to sleep (for another second) when nothing is detected and that could still result in a very low average battery current. I once made a gadget using an MCU which wakes up briefly every 8 seconds and it lasts years on a set of AA alkaline batteries.

Answer 2

Microchip does not normally specify exactly how much "more current than is specified" actually is, when an intermediate voltage is applied to a digital input. However, I've seen one situation where they had to do so - there was some part (I'm pretty sure it was in the 16F series, but don't recall which one) that had a bug in the first silicon revision, that caused the digital input buffer to still be active on one of the pins, even when it was configured in analog mode. In order for the designer to be able to make an informed decision between a potentially expensive board redesign, and simply living with the extra current draw, the errata sheet for this chip did give a specification for this: 1 mA per pin worst case (with no specification given for the exact voltage level that gives this current).

Of course, there's no guarantee that the value would be the same for the specific chip you're using, but I think it gives a rough idea of what sort of problems you'd see. I wouldn't expect there to be any danger of actual damage to the chip, but 1 mA extra draw could completely wipe out the power savings from running the chip in sleep mode.

Answer 3

This raises a few questions, most notably, what does this actually mean, and also why?

There will be an inverter at the input. If a voltage far from the supply rails appear at the input, then both the upper and lower transistor turns on, effectively causing a short circuit through the supplies. The exact current will strongly vary from chip to chip and it also strongly depends on the input voltage.

is this going to damage the chip by causing too much current draw?

No. For any short period of time it does not cause damage. The worst thing, which could happen is that the threshold voltage of the transistors shift due to hot carrier injection, but it is a long term process. Do not worry about it, unless you operate the circuit intentionally under this condition.

Or is it actually just a warning that the overall power consumption may go up compared to what the datasheet indicates?

Yes.

What if I instead wanted to connect a 3.3V digital output from another chip to it, would the same issue apply?

As long as your GPIO pad has a 3.3V or lower supply voltage, it will work as expected. On the other hand if you use 5V supply for the GPIO, then it could be considered an invalid logic level and you get into the same situation as with "analog" voltages.

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Proposed solution:

One way to overcome the issue is to add either an analog (difference) amplifier which compares the input voltage to a reference, or even to put a comparator with a reference before you GPIO input pin. In the former case the inverter of the PAD will do the digitization, but the high analog will most probably shoot the voltage at the GPIO input to one of the rails. Although an inverter, which is also in the GPIO pad can be considered as a comparator, it has no reference input and its threshold voltage varies a lot, plus its current consumption is out of your control.

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Closing notes:

• Yes, I consider both VSS and VDD as supply rails.
• The difference between analog and digital is a question of interpretation. Every physically existing signal is analog as well, just as any voltage level can be considered a digital signal, which could be an invalid one as well. The difference is at the abstraction level and how you treat the signal in your design.