How can I determine the proper value for a pull-up resistor that's being used as an input to a CD4078 when the datasheet doesn't mention anything about input impedance? I'm trying to minimize power usage since my circuit will be powered by a battery.
The datasheet does say that the input current is +- 10mA, so should a 100K @ 5V suffice since that should provide 50mA?
Considering strictly static DC operation for these CMOS gates...
Input current at maximum temperature tops-out at one microamp. So a large-value resistor of about 3 MEGohm will ensure a logic high, if no other current paths are present.
So why might you use a smaller-value pullup? A few reasons:
Noise pulses from nearby traces might momentarily yank a high-resistance pullup low.
If an open-collector (or open-drain) is to drive this input low, its leakage current would require a smaller-value pullup resistor.
A large-value pullup resistor pulls up rather slowly in the presence of capacitance. The capacitance of the input alone might be about 7pf. A slow transition time can cause logic gates to go squirrelly, and oscillate as the input slowly transits from low-to-high. A clean logic transition is often required.
The logical solution to these problems is to lower the value of pull-up resistance.
Consider that an input pin that spends most of its time "pulled-up" to logic high causes almost no current drain. You can choose a smaller-value pullup resistor, with almost no down-side.
If the pulled-up input spends most of its time low (pulled down by some other source) then current does flow, and a large-value pull-up resistor value should be chosen to reduce battery drain.
The datasheet states clearly that the maximum input current is 1μA when the input voltage is limited to be not less than 0 and not more than VDD. This is the current value to use when calculating a pullup resistor value.
The 10mA limit applies for any input voltage, and in particular it applies when the input voltage is less than 0 or greater than VDD. In that case the ESD protection diodes at the chip inputs will be forward biased and the current must be limited to prevent damaging those diodes.
