Blocking and nonblocking statements for counter

Question

Is there any difference between nonblocking and blocking assignment for the following counters?

module  nonblocking_counter (
  input clk,               
  input rstn,              
  output reg[3:0] out
);    

  always @ (posedge clk) begin
    if (! rstn)
      out <= 0;
    else 
      out <= out + 1;
  end
endmodule

module  blocking_counter (
    input clk,              
    input rstn,
    output reg[3:0] out              
);   

  always @ (posedge clk) begin
    if (! rstn)
      out = 0;
    else 
      out = out + 1;
  end
endmodule

Possible duplicate of Difference between blocking and nonblocking assignment Verilog — dave_59, Oct 15 '18 at 03:52
Actually, it is not. I understand the difference between them. I think in case of counter the behaviours are equal, am I right? — delkov, Oct 15 '18 at 06:05

score 1 · Answer 1 · answered Oct 15 '18 at 14:59

1

The circuit generated by synthesis tools will be identical for this code. However in simulation, you have a race condition on the output that feeds the input of another synchronized process when using blocking assignments.

answered Oct 15 '18 at 14:59

dave_59

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Blocking and nonblocking statements for counter

1 Answers1

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