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Is there any drawback to a longer SJW vs a shorter SJW?

The PIC32MZ2048EFH064 has a minimum phase 2 requirement of two time-quanta. This means that the SJW could be one or two time-quanta. Why wouldn't an SJW of two not be used by default?

Similarly, if phase 2 is eight time-quanta why not use an SJW of four?

vini_i
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1 Answers1

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Depending on the peripheral reference clock, its possible prescaler, and the certain/target CAN speed you need, you need to configure the PHASE_SEG1 and PHASE_SEG2 duration--expressed in integer multiples of Time Quanta (tq)--so that in a nominal case (without adding/subtracting up to SJW tq's) the position of Sampling Point to be as close as possible to 87.5% of the nominal bit time.

In the picture below, it is assumed that the nominal bit time consists of eight (8) tq's. But in your particular design it could consists of any (of course, appropriate) number of tq's depending on the conditions listed above.

Example of Bit Timing

Therefore, for example, with a nominal bit time of 10 tq's at a prescaler of N/2, you could have another option with a nominal bit time of 20 tq's (twice bigger) at a prescaler of N (twice lesser), but of the same physical duration on the wire.

SJW is an additional, "independent" parameter related to a "real" situation on the bus and defines the number of tq's up to which the PHASE_SEG's could be variated ("tuned") depending on the real situation during the transmission/reception of each bit in the message.

Generally speaking, the PHASE_SEG1 duration could be prolongated by up to maximum SJW duration while the PHASE_SEG2 duration could be shortened by SJW down until to zero (but non less than zero).

The goal of such a "tuning" is to place the Sample Point into the "good" moment and to (re-)synchronize the "collective" behavior of nodes on the bus.

The cause of such a "tuning" lays in the recessive/dominant method of transmission on a CAN bus, during that, the real transition on the bus can take place far beyond the SYNC_SEG phase duration where it is assumed to be in the nominal case.

Is there any drawback to a longer SJW vs a shorter SJW?

A longer SJW could result in a more robust interaction, a shorter SJW could result in a faster transmission. Knowing nothing about a particular bus implementation, speaking on a drawback is a clear speculation having no ground under it.

Why wouldn't an SJW of two not be used by default?

At one time-defining profile and with one bus specifics it may be of one, at another time-defining profile and/or with other bus specifics it may be non-of-one. Neither default value is less speculative...

asndre
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  • The device I'm making would be connecting to an unknown bus with a known baud rate. I'm trying to maximize my chances of a successful connection. How would a short SJW make transmission faster? – vini_i Sep 12 '18 at 17:05
  • @vini_i Simply/roughly speaking, any node on the bus---including a (the) transmitting node---could perform a resynchronization during any bit transferring. Such a resync could lengthen the PHASESEG1 up to SJW. Thus the longer the SJW, the longer the PHASESEG1 and the slower the transmission. – asndre Sep 14 '18 at 19:07
  • @vini_i CAN Spec 2.0 defines (see Part A - Page 29): The RESYNCHRONIZATION JUMP WIDTH shall be programmable between 1 and min(4, PHASE_SEG1), speaking nothing on "default value". Meanwhile this doc (see 2.5), for example, notes that "It is recommended that a large Resynchronization Jump Width be used". – asndre Sep 14 '18 at 19:13
  • @vini_i To maximize the chances of a successful connection, you could implement this (SJW) parameter configurable in your Controller and transfer the choice and responsibility to the (end) user, or could make it constant as long as possible per the Specification (SJW=max{4, PHASE_SEG1}) if you believe in the authority of the exampled source. (or find other source you could believe to.) – asndre Sep 14 '18 at 19:18
  • Should phase 1 then be symmetric to phase 2? – vini_i Sep 14 '18 at 19:18
  • @vini_i there is no such a req in the Spec, see Ch 8, "BIT TIMING REQUIREMENTS". – asndre Sep 14 '18 at 19:22
  • What would be the difference between a long propagation delay and short phase 1 vs a short delay and long phase 1? Assuming that the total TQ and phase 2 remain the same. – vini_i Sep 14 '18 at 19:27
  • @vini_i If you mean "phase 1" is "the time before sampling point", then it consist of three SEGs (see Spec): SYNC_SEG + PROP_SEG + PHASE_SEG1, i.e. "phase 1" > PROP_SEG (propagation time) in any case of proper operation. if you expect that the prop delay will be greater than the "phase 1" of the initially selected speed, you need to lower the speed to match the "phases" with the bus specific properly. – asndre Sep 14 '18 at 19:37
  • Functionally what would be the difference between 1+6+1+2 vs 1+1+6+2 for sinc, prop, ph1, ph2 respectively? – vini_i Sep 14 '18 at 21:35
  • Where does 87.5% come from? – Peter Mortensen Sep 16 '18 at 09:30
  • @vini_i Functionally: SJW=max{4, PHASE_SEG1}. If PHASE_SEG1=1 then SJW=max{4,1}=1. If PHASE_SEG1=6 then SJW=max{4,6}=4. – asndre Sep 16 '18 at 12:21
  • @PeterMortensen From here. – asndre Sep 16 '18 at 12:25
  • So ph1, ph2 need to be symmetrical for SJW? If ph2 is 2 then ph1 also needs to be 2 for an SJW of 2. – vini_i Sep 16 '18 at 12:38
  • @vini_i Per Spec: IPT={0;1;2}, PHASE_SEG2=max{PHASE_SEG1, IPT}, SJWmax=min{4, PHASE_SEG1}. With PHASE_SEG1=2, PHASE_SEG2=2, SJWmax=2 (i.e. SJW could be any in {1; 2}). – asndre Sep 16 '18 at 13:11