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I have several questions about how I would design my own ARM-based CPU?

  • How does one start with an ARM license and end up with a package ready to be soldered on to a board?
  • What do I get from ARM (I am sure they have multiple license options to dish out - Architecture License (Qualcomm Snapdragon style) and Core License (TI OMAP style))?
  • What tools do I need to proceed once I have 'that something' from ARM?
  • What do I send to the fab?
  • I believe only certain foundaries are licensed to etch an ARM core on to a silicon wafer. Am I right?
  • As a student, can I afford to do this on an FPGA? How do I get hands on experience for something like this?
Renan
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Lord Loh.
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    Did you talk to ARM? [Edited by a moderator.] – Olin Lathrop Aug 03 '12 at 19:41
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    Take a look at http://www.opencores.com -- there are lots of various processor cores there in various states of completeness and functionality. As far as obtaining actual ARM core source... as @OlinLathrop says... talk to ARM. – akohlsmith Aug 03 '12 at 19:46
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    I don't understand the downvotes, this is may be a naive question, but definitely legitimate IMO. – Jon L Aug 03 '12 at 20:09
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    @JonL - Thank you for understanding. I did frame it naively so as to get maximum explanation. My maximum experience is writing some verilog code for DSP projects and some CISC & pipelined RISC processor (grad school project level complexity) – Lord Loh. Aug 03 '12 at 20:34
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    @JonL: Because the obvious answer is to ask ARM. At best we are just speculating, unless someone here happens to work for ARM and knows what options are available. -1 since it appears there was no attempt to follow the obvious path or that any research at all was done. – Olin Lathrop Aug 03 '12 at 20:38
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    @OlinLathrop - Since I am not going to be buying an IP, I doubt that an ARM representative is going to waste his/her time talking to me. Kindly point me some non-obscure resource over the internet that one might come across while researching. I was hoping that someone here might have some experience with the Architecture -> Si or Core -> Si workflow. – Lord Loh. Aug 03 '12 at 20:52
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    As you've now confirmed the apparent implausability of the project by outright stating that you aren't going to buy the IP, what exactly is the point of asking a question that is inseparable from buying that particular IP, rather than a generic one? – Chris Stratton Aug 03 '12 at 21:00
  • @ChrisStratton - Academic interest! I could start from scratch with my own design, but I do not want to remain ignorant of the workflow. Should I be hired on to design an application processor, such an insight shall be useful. Moreover, how likely is one going to use a tool (an ARM core / architecture), if one is unaware of it's existence, benefits or knowledge of how to use it. – Lord Loh. Aug 03 '12 at 21:06
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    The problem is that your question is specific to a workflow you will not get to follow. The workflows you can follow - using an original or freely available design in an HDL to target an FPGA - are as different from that as speculation is from fact. – Chris Stratton Aug 03 '12 at 21:14
  • I understand that I could possibly not get an ARM into an FPGA. From what you wrote, it sounds like if I choose a MIPS core, I would have a different work flow. Will I?

    If I used a Xilinx Zynq, can I experience a part of that workflow?

     – Lord Loh. Aug 03 '12 at 21:45
  • @ChrisStratton - The Zynq development board - Do you think this can be a partial experience of designing around an arm core? (Core License) http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1028&Prod=ZEDBOARD – Lord Loh. Aug 03 '12 at 22:07
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    The Cortex-M1 core seems to be intended to run in any suitably capable FPGA. The major FPGA vendors have the IP license, and deliver it to the designer as they would any other soft core. I assume not for free, but there are likely programs available specifically for academic use. – RBerteig Aug 03 '12 at 23:22
  • I recently came across this read. Gives you some nice overview of how ARM business model itself works, what kind of licenses they give out and their rough cost. https://www.anandtech.com/show/7112/the-arm-diaries-part-1-how-arms-business-model-works/3 – Hotsndot Dec 30 '20 at 11:37

5 Answers5

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Here is how companies do it:

  1. Raise about US$10 million.
  2. Negotiate with ARM to get a license. This will probably cost at least US$1 million.
  3. Get the design files from ARM. It will likely be in some form of VHDL, Verilog, or an "encrypted" netlist.
  4. Design your own chip using a mix of your own logic (for the peripherals) and what ARM gave you. This step will likely require some expensive CAD software and a small team of experts. Expect to spend at least US$5 million and several years.
  5. Get the masks made for the chip itself. If you use any modern semiconductor process then this will run around US$1 million.
  6. Get the chip itself made. Price varies, but should be less than US$0.5 million.
  7. Debug the chip you created, fix the bugs, then go back to Step 5 until you have something that you can sell.

Here is how YOU do it:

  1. Take a graduate level computer architecture course at your local university.
  2. Take more courses in digital logic and whatever else.
  3. Design a CPU from scratch in VHDL or Verilog.
  4. Design another CPU from scratch.
  5. Look at the ARM instruction set and design a compatible CPU.
  6. Make your ARM-Compatible CPU work in an FPGA.
  7. Don't distribute your VHDL/Verilog source code unless you want to be sued.
  8. Use your ARM experience to write a good dissertation for your PhD.
  9. Use your PhD to get a job at ARM, or TI, or whoever. Then repeat the process using the previous 7 steps on how a company does it.

Ok, so this list is a little tongue-in-cheek but it is basically correct. The point is, don't even bother dealing with ARM directly because odds are you don't have the money. And don't do anything that will get you sued by ARM either.

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    +1. Excellent answer. What I was going to say, but better. – Rocketmagnet Aug 03 '12 at 20:08
  • What do you think should be included in a graduate level computer architecture course? As our computer architecture module didn't tell us much about design more theory less practical as such. – Dean Aug 03 '12 at 20:11
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    Any good course would include the basic structure of different kinds of CPU's and how they all work. Topics should cover microcode, instruction decode, ALU's, memory access, cache, registers, pipelining, data hazzards, instruction prefetch, etc. –  Aug 03 '12 at 20:19
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    Is there any reason that the ARM's instruction set, in and of itself, would be any more patentable than any of the other CPUs of which clones abound? Certainly there are apt to be some architectural features that are patented, but if one's goal is to design a CPU which will work with existing compilers, would the instruction set itself pose a problem? – supercat Aug 03 '12 at 20:23
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    @supercat Normally instructions themselves are not very patent-able unless they incorporate some architectural things. MIPS did this with their CPU's, where they patented some instructions that would load/store words that are not word-aligned as well as some stuff to dynamically switch between big and little endian. This was challenged in court when MIPS sued a MIPS clone maker, and MIPS won (back around 2000). But most patents are about architectural issues. You can't make a CPU that is compatible with existing compilers without copying both the architecture and instruction set, sadly. –  Aug 03 '12 at 20:33
  • @DavidKessner - Great answer. Could you suggest some tools that are actually used. I did look around on the product sections of the 'Big Three' (Synopsys / Mentor / Cadence) and got lost in their design tools arsenal - Functional Verification products, Physical Verification Products, Logic Design. I could not even correlate the products from one of the big three EDA co. with their counter part from the other EDA Co.

    Are using these tools taught at Universities? How does once get around learning this?

    I am in a PhD program at Texas Tech U., but it does not involve architecture.

     – Lord Loh. Aug 03 '12 at 20:48
  • @DavidKessner: I don't think most compilers dynamically switch endian-ness or do other such things, do they? I would think it should be possible to pick out a subset of the ARM instruction set to which compilers could be told to restrict their output, but which didn't incorporate any forbidden features. The concept of allowing word loads from possibly-misaligned addresses was demonstrated in 1978 if not before (Intel 8086), so if one isn't dynamically changing endian-ness I wouldn't see any problems there. Do you have any references for what exactly ARM is claiming? – supercat Aug 03 '12 at 20:49
  • The Architecture course at my university taught just that - we implemented a RISC in Xilinx ISE Web pack and attempted to prove it using modelsim - nothing was implemented on a real FPGA. The pipeline hazard discussion was just theoretical. The only tools used was the ISE Webpack and modelsim. At the end of the class, I was not even aware of professional workflow that Qualcomm or TI like Co. use to roll out their products. – Lord Loh. Aug 03 '12 at 21:02
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    @LordLoh you may find these questions useful: http://electronics.stackexchange.com/questions/28686/how-is-asic-design-different-from-fpga-hdl-synthesis/28693#28693 http://electronics.stackexchange.com/a/7051/638 – W5VO Aug 03 '12 at 21:08
  • @LordLoh. that sounds like the undergraduate computer architecture class I took, I hope it was one for you. – Kortuk Aug 03 '12 at 21:17
  • The Computer Engineering course that I did implemented a CPU in VHDL. It wasnt just one module but a series over the 3 years. Those that passed all the tests actually got fabricated over the summer too! One of the lecturers was actually a designer on the original BBC micro - so the department had links to ARM. – Dave Hillier Aug 04 '12 at 09:32
  • And this isnt ARM, but MIPS threatening about opencore designs http://brej.org/yellow_star/letter.pdf – Dave Hillier Aug 04 '12 at 09:37
  • I'm not surprised. I actually talked with Damjan Lampret about 10 years ago when OpenCores started. At the time I had just finished my own MIPS core but had decided to not release it based on the threat of lawsuit. I advised Damjan to avoid stuff like that too, but he obviously didn't listen. –  Aug 04 '12 at 14:06
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ARM has a University DesignStart Program. As a student, you can only access basic Cortex-M0 material. But if you are really interested, get your faculty involved and then you can have access to much more design material (Verilog FPGA code, Evaluation IP, Simulations, etc.)

embedded.kyle
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5

Take a look at this ARM core on OpenCores.

Renan
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plan9assembler
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    But be warned: such re-implementations are merely tolerated by ARM: http://www.eetimes.com/author.asp?section_id=36&doc_id=1287452 , you will be a cease-and-desist / lawsuit away. Also consider open archs like RISC-V. – Ciro Santilli OurBigBook.com Jun 20 '16 at 14:55
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The ARM Cortex-M1 (probably the simplest of the ARM processors) is the first ARM processor specifically designed to be implemented as a soft processor in FPGAs. It is optimized for the following FPGA types:

Actel (M1 ProASIC3 and M1 Fusion)
Altera (Cyclone-II, Stratix-III)
Xilinx (Spartan-3, Virtex-5)

ARM itself is making a Cortex-M1 Development Kit for Altera Cyclone III although it is a little pricey at $625 from DigiKey. You do get all of the ARM Cortex-M1 IP though, and a license to do development (plus a free royalty grant for 1000 boards for those going into production, pretty cool).

There may be some options for getting the IP by itself (perhaps they have an academic program, someone else mentioned a university program, but that was for the M0). Then you could buy a development board separately.

Here is some more information about the ARM Cortex-M1 on Altera.

Here's some information about putting a ARM Cortex-M1 on an Actel FPGA.

Meanwhile there is some interest in other versions of the ARM Cortex on FPGA; here is a paper from someone that implemented a ARM Cortex-M0 on a Xilinx FPGA.

tcrosley
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  • If you want to change the design, try making a "proper" 32-bit machine. Currently, the ARM reads 32-bit instruction 8 bits at a time, meaning the PC increments by 4 for each instruction fetch. – Alan Campbell Nov 08 '14 at 02:49
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You can now get access to the Cortex-M3 processor (and an extendable AHB/APB subsystem) through ARM's DesignStart program.

The Eval option provides an FPGA target (simulation is supported, with obfuscated RTL of the core, everything else in Verilog). This currently targets the ARM MPS2+ FPGA, with mbed support.

The Pro version (only available to companies/universities who can sign a license) allows manufacture, and includes the processor core in Verilog (this covers both Cortex-M0 and Cortex-M3).

Sean Houlihane
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