How to draw a timing diagram for CSE 120 class

Question

I've never done a timing diagram before. So I basically have no idea what I'm doing or what the question is asking. I would appreciate any help! Thank you.

Answer 1

For part a) ignore the PRE' input signal. Add to the timing diagram a new trace labeled 'D.Q' that shows the logic signal one would expect to see at the Q output of a D-type ("data") flip-flop for the given clock, D, and CLR' input signals.

For part b) add to the timing diagram a new trace labeled 'T.Q' that shows the logic signal one would expect to see at the Q output of a T-type ("toggle") flip-flop for the given T, CLR', and PRE' input signals.

Hint 1: Does a T ("toggle") flip flop have a clock input?

Hint 2: The "D or T" signal is applied to the DATA input on the D flip-flop, and to the TOGGLE input on a T flip-flop.

Hint 3: What does "assume negative edge trigger" mean for a T flip flop?, and which of the traces in your figure provides the "negative edge trigger" for the T flip flop?

Hint 4: Is the value of D.Q and T.Q known for all times t along the timeline, or are there places where the value of D.Q or T.Q is indeterminate? For regions where the value of D.Q or T.Q is indeterminate, draw a box filled with an 'X' ("don't know") rather than a logic HIGH or LOW trace.