PMOS Falling Time

Question

I have established a circuit which has a -7V,+7V 16kHz square wave and my aim is obtaining 0V,+1V 16kHz square wave output signal. To do this, i have used a TI SN75189ADR and DMP4051LK3-13 pmos as i mentioned below;

Because of the inverting function of the SN75189ADR, i used pmos for switching and with a voltage divider configuration, i have tried to obtained 0V,+1V square wave. I have almost reach my goal however there is a long falling time as 4.4 us at the output. I have shown below "±7V_SQUARE_WAVE_INPUT" as yellow signal and "MOSOUT" signal as blue;

I have realized that the low falling time is also at the "RCOUT1". I think the output of the SN75189ADR is dependent to its load. I have changed the pmos but the lack was still there. Do you have a suggestion about how i can decrease the falling time on the PCB (I can use some capacitors or resistors on board but i can't change the configuration because PCB was produced.)? Thank you.

Answer 1

The problem is most likely the SN75189. It has an BJT to pull the output low, but only an 1.66k resistor pulling up. Which means it will take a lot of time to discharge the gate capacitance of the FET. I would use another chip that can do the 7V->1V directly. Or if you cannot find one, there are easier to do transistor based circuits that one can use.

Answer 2

Low RdsOn FETs (85 mΩ) have high input capacitance (674 pF typ) and TTL with ~ 5K pullup on open collector is a poor drive source here.

Use my Rule of Thumb on drive out/in impedance ratio. I usually limit this impedance to 200:1 for a more ideal response. Not to mention impedance is asymmetric on both inputs and outputs.

You would get a better response with a CMOS buffer.

Your impedance ratio source/out for logic "1" is 5kΩ/85 mΩ or almost 60k:1 , so it is slow !

Your RC time constant 674pF(@ 0Vgs) * 5k = 3.3us which is close to your fall time and you also have high latency.