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I have a question about how process state would be saved during a context switch.

Given a relatively simple design for a CPU using von Neumann style architecture, how is the process image saved without overriding some of that state in the process?

For example, if I want to save the current state of all registers including the program and memory address registers, how can I write them to a memory location without overriding the stack and base pointers in the process?

Is there auxiliary hardware that holds intermediate values, and if so what does it look like in a more simple sense compared to the industry standard?

Jack
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  • A relevant SO question. In x86, "TSS" - Task State Segment is the keyword that you might want to search. – uint128_t Apr 16 '17 at 23:48
  • There was a processor which did context switching with a combination of hardware and microprogramm. There was a hardware register for the process number and the sequence of processes could be measured with external hardware like a logic analyzer. But this was not a microprocessor, the processor was build using hundreds of chips and tenth of boards. – Uwe Apr 17 '17 at 14:25

2 Answers2

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Speaking very generally, the most common approach is to push the process state onto its own stack, and then switch stacks by updating the stack pointer to the value saved for the next process to be executed. After the process state is restored from this stack, everything — including the stack pointer itself — is restored to the values they had the last time this process was running.

The operating system maintains a table of data in which each entry represents a process in the system. In addition to storing the stack pointer for each process, it has flags indicating whether the process is active or suspended, what the process's priority is relative to other processes, and what sort of events can "wake up" a suspended process.

Dave Tweed
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Both options exist, of dedicated hardware and general-purpose approaches.

X86 real mode (see description) uses the currently setup stack to push FLAGS, followed by CS, then IP.

The iret instruction restores CS:IP and FLAGS, allowing the interrupted program to continue unaffected. For hardware interrupts, all other registers (including the general-purpose registers) must be explicitly preserved (e.g. if an interrupt routine makes use of AX, it should push AX when it begins and pop AX when it ends). It is good practice for software interrupts to preserve all registers except those containing return values.

Obviously this process changes the stack, but in a reversible way.

By contrast, ARM FIQ mode (see https://stackoverflow.com/questions/973933/what-is-the-difference-between-fiq-and-irq-interrupt-system ) has a set of banked registers. On entry to FIQ mode the processor automatically swaps to using the banked registers. This saves on memory accesses.

Community
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pjc50
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