What is the influence of an asymetric load capacitance on a crystal duty cycle

Question

I have a crystal oscillating at 25MHz (datasheet). The recommanded load capacitance is 18pF according to the datasheet.

The crystal is connected to a component where the capacitance on the pin are not the same : CIO1 = 11pF and CIO2 = 8pF.

I did the calculation to determine what capacitor was needed to connect on the pin :

With 11pF and 8pF on the IO pin the equivalente capacitance is 4.6pF then :

C_x=2*(C_L-C_p)

C_x=2*(18-4.6)

C_x=26.8pF

Then I selected two capacitors of 27pF to connect from each side of the crystal to the ground.

My problem is, since the capacitance on each pin is not the same I believe the duty cycle will not be 50%, because on one side the crystal has a 11+27=38pF and on the other side 8+27=35pF.

Knowing that, how can I theorically calculate the duty cycle?

Answer 1

It doesn't work how you are imagining.

A crystal only sees one load, which ideally has the impedance specified in the datasheet. In this case, that impedance is 18 pF. That causes the right phase shift when used with the right driving circuit (inverting in this case) so that the circuit will oscillate, and the oscillating frequency will be within spec.

You are somehow imagining that the caps on the input and output of the crystal are "load" caps. This is not the case. The one on the output is, along with whatever stray capacitance there is. The one on the input is mostly for the purpose of attenuating the harmonics produced by the drive circuit. Most of these circuits are basically digital inverters, and try to create square waves. The first cap is to make that signal more of a sine wave.

There are two reasons for wanting to drive the crystal with a sine wave. First, it reduces the overall drive to the crystal by giving it only the signal you want it to handle. Crystals can be overdriven, which can damage them and result in out of spec frequency. Seconds, it keeps the crystal from oscillating at one of the harmonics of the intended operating point. You only want greater than unity loop gain at the desired frequency. If you have greater than unity gain at higher frequency, you run the risk of the crystal resonating at one of its harmonics. In some cases this effect is harnessed deliberately to get high frequencies, and is called overtone operation.

If the input to the crystal had 0 impedance, meaning it is being driven by a perfect voltage source, then the output only needs to be connected to the specified load capacitance. Some stray capacitance will always be there, so the deliberately added capacitance should be a little lower.

When the input is not 0 impedance, then the load capacitance should be increased to compensate. Since the impedance of the crystal driver output is usually poorly known, you guess. 22 pF on both input and output usually works pretty well for "18 pF" parallel resonant crystals.

None of this has anything to do with duty cycle. The very high Q of the crystal causes all frequencies other then the oscillating frequency to be greatly attenuated. This leaves only a sine. The output of a crystal always has a sine shape on it, unless you are seriously abusing the crystal. Different load caps won't change this. They only affect whether there is enough loop gain to oscillate at all, and whether the resulting frequency will be within spec.

Answer 2

There seems to be few misconceptions here. The crystal is not "driven by" sine or square wave from the driver. The Pierce oscillator is a positive-feedback self-oscillating circuit with non-linear effective gain. The gain depends on where the input DC working point is settled to. Depending on feedback network parameters (crystal and load caps, with characteristic impedance at resonance point), the resulting amplitude may settle to a nearly sinusoidal form (which is good for frequency stability), or be more "squarish". This self oscillating circuit usually produces well balanced waveform, but its peak-to-peak output amplitude is always smaller than Vdd power rail.

The duty cycle of internal clock, however, depends on how this oscillator is interfaced INTERNALLY, depending on switching threshold of the follower. In many cases the original duty cycle does not matter for digital design purposes, since the usual design technique is to divide that clock by 2 and have a perfect duty cycle before it enters internal PLLs or else.