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I'm studying the MIPS CPU and I have a very basic question about the datapath. Since the MIPS CPU uses a 5 stage pipeline, that means that the pipeline is using a multicycle datapath, correct? If a CPU has instructions where the Cycles Per Instruction is greater than 1, the CPU is using a multicycle datapath. Correct?

I guess I'm trying to understand if there's ever a case where you can have a pipelined CPU that's NOT using a multicycle datapath. In my mind, pipelining always implies a multicycle datapath. Is that the case? Or are there exceptions?

mjh2007
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    Where I'm getting confused is here "unlike the multi cycle cpu, the pipelined datapath requires that every instruction use all five stages of execution."(1) This implies that the multicycle and pipelined datapaths are two different things. So if someone says " The MIPS 5-stage pipeline system uses the multi-cycle datapath", based on my initial understanding, the answer would be true. But based on the quote, the answer would be false. Can someone clarify?

    (1) http://cseweb.ucsd.edu/~j2lau/cs141/week6.html

     –  May 04 '10 at 02:57
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    I see what you are trying to learn here, but this is the second time I have seen a question that is clearly for a class. I think just asking a class question here does get a quick answer but this is a disservice to you and to the people answering. You learn a very large amount about devices and systems through the process of researching a question. People on here spend time doing your homework. You are shorting yourself of education and members of this forum of their time. – Kortuk May 04 '10 at 06:46

2 Answers2

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A pipelined CPU implies a multi-cycle datapath, precisely because it takes five clock cycles for an instruction to go from Fetch to Writeback.

Where I'm getting confused is here "unlike the multi cycle cpu, the pipelined datapath requires that every instruction use all five stages of execution."

You should finish reading the next paragraph you're quoting. That requirement is just to prevent two instructions from finishing at the same time.

suppose we use the latencies from our multi-cycle cpu, and we try to run a load instruction followed by an add instruction. the load instruction will require five cycles to execute, and the add instruction will require four cycles. so, if we start running the load instruction on cycle 1, it will finish execution on cycle 5. we are pipelining, so we can start running the add instruction on cycle 2, and it will finish on cycle 5. this is a problem: we have two instructions finishing on cycle 5: they will both try to write to the register file on cycle 5. this is a problem, because our register file only has one write port.

ajs410
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Many of the old 8 bit microprocessors (before the 8086, let's say) had instructions that took more than one cycle to execute and no pipeline capability. Each instruction would go through fetch, decode, execution, and write-back phases, but each one would run to completion before the next one could start. A bit like having a highway from NY to DC and only letting one car on it at a time.

Pipelining takes advantage of the fact that you could, for instance, be using the instruction fetching logic to get the next instruction while executing the current one. This is know as instruction level parallelism, since you have more than one instruction executing at a time. Now in the highway analogy, you don't have to wait for the 1st car to arrive in DC before letting another one on at NY. This sort of thing started happening around the time of the 8086/8088. (and there were no doubt others, but I offer the 8086 merely as a reference point in time)

So, no, having instructions that require more than one cycle does not imply pipelining.

On the other hand, if all your instructions could be executed in a single cycle, there would be no advantage to pipelining, as there would effectively be no way to run different stages of different instructions at the same time. So pipelining seems to imply that instructions can be decomposed into different phases that can be parallelized.

(It's actually hard to envision what kind of instruction could be done in a single cycle, beyond a simple NOP. Even plain register-to-register transfers would require one cycle to pull the opcode into the chip and another cycle to achieve the effect.)

JustJeff
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  • most processors/controllers today still have instructions that take more than one clock cycle, even in a pipeline. – Kortuk May 04 '10 at 10:57
  • OK, I understand that multicycle doesn't imply pipelining but does pipelining imply multicycle? In general, pipelining uses multiple cycles so there's a lot of similarity but from the link above, the pipelined datapath and the multicycle datapath are very different. This is what I was trying to confirm. –  May 04 '10 at 11:57
  • @Henley: my take on it is that pipelining does imply multi-cycle instructions, otherwise, how can you pipeline? – JustJeff May 04 '10 at 21:30
  • @Kortuk: I didn't mean to imply modern CPUs don't have multi-cycle instructions, it was a hasty bit of writing I've edited a little, hopefully makes more sense now. – JustJeff May 04 '10 at 21:31
  • I had a feeling you knew that, JustJeff, but others may not. – Kortuk May 04 '10 at 23:27
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    FYI, the 6502 (mid 1970's) fetches the second byte of each instruction while decoding of the first one (if the second byte isn't needed, it's discarded), and overlaps the register write-back (if necessary) with the fetch of the first byte of the next instruction. – supercat Mar 01 '11 at 15:35
  • @JustJeff - actually, it's entirely possible to build a cpu in which the program counter updates on a clock edge, its value becomes the address input to the program memory, whose addressed contents propagate through the instruction decode logic, become register file or (harvard) data memory address inputs, register/memory operands propagate through the cpu, and results and next pc value are ready to be latched to the next clock edge. Such a device would be slow given the long propagation chains, but conceptually quite simple. – Chris Stratton Jun 04 '11 at 02:15