0

When reading about 74HC161 synchronous counter, I understood almost everything except how the carry look ahead logic works. As far as I can see, when the counter reaches 1111, the TC pin is set to 1 for a certain amount of time. How does that help in n-bit cascading and what is the purpose of the carry look ahead in general? Thanks!

http://pdf1.alldatasheet.com/datasheet-pdf/view/15545/PHILIPS/74HC161.html

Martin Nikovski
  • 39
  • 4

2 Answers2

4

Fortunately I have the books on the 74HCxx and 74ACxx series, which show the internal logic of the 74HC161 IC's. As a single IC, the CET (count enable toggle) pin must be high for a clock pulse at the CEP (count enable pulse) to be counted.

1) Pin TC is high at full count only, and for multiple counters connects to the CET input of the next stage (IC). Internally the CET gates the CEP input and goes to a 5 input AND gate who's output is the TC pin. This AND gate outputs a logic high only if the count is full and the CET input is high due to a previous stage being at full count.

2) Since the clock is common to all CEP pins only the stages with CET = high will count. It is a carry look-ahead scheme in that the internal logic of each IC makes sure the next stage counts up by one if the preceding stage is at full count.

3) Since the CET pin feeds a signal to all downstream stages, any 'next stage' counter that is at full count will roll over to '0000'. This 'roll-over' action stops at the first counter that is not at full count. Instead it will count up by one. Because it does not have CET = high, the following stage will not count up, but maintain their current value.

4) This way a string of these IC's will count up from zero properly, and when all of them reach maximum count, will all roll over to zero at the same time, and count up again as long as the clock pulses continue.

5) This carry look-ahead scheme works because as the next stage is counting up (or rolling over to zero), the previous stage which was at full count with the TC pin high will also roll over to zero. That is why the TC pin is set high before the next clock pulse (at full count), hence the 'look-ahead' description and method.

0

Look here http://datasheet.elcodis.com/pdf2/81/57/815756/sn54hc161.pdf On page 11 is a circuit using several 74HC161 with the connection of RCO to ENP and ENT. See page 12 for a glitch of RCO and the maximum frequency of clock.

Uwe
  • 2,813
  • 1
  • 11
  • 18
  • A URL by itself is not a good answer even if it helps. URL's are time dependant, meaning that a year from now it is gone, making the answer a moot point. Elaborate or copy and paste more details of your explanation so your answer will be understandable if the URL link is no good. –  Jun 26 '16 at 17:36
  • Note that 'RCO' is referred to as 'TC' on some datasheets. –  Jun 26 '16 at 17:38
  • Copy and paste does not help to include a screenshot of the circuit diagram as a png file. – Uwe Jun 29 '16 at 16:21
  • Then you should include such a screenshot as part of your answer, otherwise this answer is more of a comment. – user2943160 Jun 29 '16 at 16:26
  • @Uwe: You would need to take a screenshot, save to disk and then upload using the image insert button which is handy drag and drop. Welcome to EE.SE. – Transistor Jun 29 '16 at 16:41