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LTSpice has the element called Lossy transmission line (symbol name ltline):

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I tried to simalate a pretty simple schematic:

enter image description here

  • R2,R3 and R4 resistors are for solve floating node problem.

Simulation of this scheme is extremely slow (about 30us/sec). If I remove the ltline symbols and replace them with a wire or a resistor the simulation speed is a link of an eye!

However I need an element representing an electrical wire. Is there any solution?

Thanks!

UPDATE 1

After making the simulation times shorter (1ms) I received some kind of a result:

enter image description here

And I make a note that if the O1 line becomes shorter the simulation time rises.

Roman Matveev
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  • What actual system are you trying to simulat? – The Photon Jul 24 '15 at 18:43
  • @ThePhoton I tried to simulate the signal transmission over the power line. The signal source is a V2 connected to the line via C1 cap. The signl is measured at the top end of the R1 load resistor. – Roman Matveev Jul 24 '15 at 18:46
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    What is your unit of distance? The transmission line model in LTSPICE is probably meant to represent a signal line, not a power line. If your lengths are less than 1/10 of a wavelength (so less than about 60 km), I would think that just using a single lumped RLC model instead of the LTRA elemenat should get you a close-enough solution. – The Photon Jul 24 '15 at 18:51
  • @ThePhoton So is that correct that I should put R and L in a seria on the "top" line wire? And where should I put the cap? between R and L? – Roman Matveev Jul 24 '15 at 18:56
  • Please follow http://www.ecircuitcenter.com/Circuits/tline1/tline1.htm It gives better simulation speed for transmission line. –  Nov 04 '15 at 13:02
  • A true lumped element would take longer to simulate per LTspice help pages. – Smartacus Sep 18 '17 at 21:21

3 Answers3

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Simulating a transmission line is hard!

The Spice model used will be a very long array of RLC lumped elements to simulated the basic model of a transmission line. With so many elements to simulate it will take a long time. Removing the transmission line will in turn remove all the many elements and so it will speed up.

Tom Carpenter
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  • I tried to make the simulation time mush shorter (let's say - 1ms) and I make a note that the longer the line the shorter the simulation time. So fo 1 km of wire it took 10 seconds to simulate the trace, with 1m - couple of minutes. – Roman Matveev Jul 24 '15 at 18:45
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    @TomCarpenter I would be surprised if a modern SPICE implementation used a long RLC network to simulate transmission lines. A much better solution if you don't care about the actual state inside the transmission line is to use a 2-port network which captures the solution to the telegrapher's equation: see here – helloworld922 Jul 24 '15 at 19:14
  • @helloworld922 As far as I remember when playing with LTSpice it uses an RLC ladder. If someone knows for definite please do correc me. A 2-port approach would be better but I don't recall LTSpice being that complex. – Tom Carpenter Jul 24 '15 at 19:23
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The telegrapher equations do not capture the actual delay in the propagation down the line. They only capture phase and loss. The typical two port model of a transmission line does this as well. As a result, this typical model is only good for steady state simulations.

Said a different way, real transmission lines have memory while simple two port models do not.

Ward
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    Incorrect. The Telegrapher’s equations do capture the delay, since they reduce to two Helmholtz (wave) equations about the current and the voltage. – user110971 Jul 10 '19 at 18:01
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My apologies for the necromancy, but the reason why the simulation goes slow is because of the delays of the transmission lines compared to the simulation time: ~14.5ns and ~1.45us, out of which the smallest one will cause the slowest simulation timestep. The internal models have nothing to do with this. The same crawl would happen if the lossy transmmission lines (ltline) would be replaced by (roughly) equivalent ideal transmission lines (tline). The solution for this (seeing the value of the input source) is what @ThePhoton mentions in OP's comment.

a concerned citizen
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  • What is the point of simulate smaller periods if the signal wouldn't even reach the other end of the line? – ZAB Sep 03 '20 at 01:40
  • @ZAB I don't understand what you mean by "the signal wouldn't reach the end of the line". All the signals end up where they're supposed to end up. The delay of the transmission line affects the simulation time, since the solver cannot use a timestep that is larger than the delay of the transmission line. – a concerned citizen Sep 03 '20 at 07:04
  • You've told that the simulation is slow because the simulation time is bigger than the line delay time. But this is the point of the long line simulation. Why would anyone simulate periods shorter than the line delay? – ZAB Sep 04 '20 at 17:19
  • @ZAB No, I said the reason why the simulation goes slow is because of the delays of the transmission lines compared to the simulation time, which is not the same. OP has defined two ltlines, with 1.45u and 14.5n delays, out of which the smallest delay (14.5n) will be the highest timestep for the total simulation time of 20m. The solver will not use timesteps larger than the delay since the rate of change is directly proportional to the delay, itself. So you got it backwards: it's not slow because the simulation time is bigger, it's because the delay is much smaller than the simulation. – a concerned citizen Sep 04 '20 at 18:16
  • Ah. I see... This makes sense ) – ZAB Sep 04 '20 at 18:29