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I have my voltage rails coming off board and I have quite a number of ICs. Each has their own decoupling and for the really demanding ICs I have a bulk capacitor.

If I have some target impedance and it's said that to achieve that impedance I need 10 capacitors of various values and sizes, where do all these capacitors sit ?

Are they grouped together ? Are they spread out over the board ? Are they near the digital ICs ? Are they placed where power enter the board ?

efox29
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  • "it's said" - please place a link to this quote. – Andy aka Jun 07 '15 at 00:16
  • It was just an example, because it depends on the target impedance so the actual number and value will vary. But here is an example http://app.pdntool.com/ – efox29 Jun 07 '15 at 00:19
  • @Andyaka If your chips can tolerate delta_V ripple with a current of delta_I, it follows that your PDN will work well if you keep the impedance across frequency below Z_target = delta_V/delta_I. – Rolf Ostergaard Jun 07 '15 at 08:32
  • @rolf was your comment meant for the op? – Andy aka Jun 07 '15 at 10:25

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Think about where would they would be placed to minimize the inductance between them and your chip. Smaller value ones being placed closer with the larger bulks a bit further away.

Often times this is directly under your bga but depending on your reference plane design it could be right at the edge of the chip. Parts with feet or qfns will want them close to the pins.

Again the goal as you said is minimize impedance wherever you can. Every connection, via, trace and plane adds impedance between you and your PDN. Think of it that way and you should be fine.

This is the reason for example you don't want to share vias with PDN caps as well as why via on side routing is prefered now.

Btw you should take those into account when calculating your over all impedance the rcl models of just the caps is not sufficient. You can make approximations if you are using spice or say an excel based PDN tool like Altera's. More solid values can be determined through a post layout simulation tool like Sigrity. If you are really working on something difficult you can measure the impedance on your boards later but the tools for that don't even rent cheaply :)

Some Hardware Guy
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With closely coupled power and ground planes, the location of bypass caps are relatively unimportant (this has been well known for more than 25 years - find the Hubling IEEE paper if you doubt that).

I have written about that and shown it with measurements as well.

That being said, my recommendation would be to spread the bypass caps across the board. Think something like a one inch grid (roughly). But get them out of the way of your routing. And don't make your power plane shape too funky.

I have just seen a 3D simulation of a board following this concept and the impedance was as flat and nice as it gets.

Feel free to use my pdntool.com tool to find a good combination of capacitors and make sure you understand how mounting impedance of the individual capacitor dominates the parasitics.

Rolf Ostergaard
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  • Fantastic. I'll be sure to get that IEEE paper. How do you determine if planes are "tightly" coupled ? So small values closer to the digital stuff and the bigger caps in between digital ? – efox29 Jun 07 '15 at 07:53
  • Tightly coupled planes will be closer than ~.15mm... typically one ply 1080 is a good solution. – Rolf Ostergaard Jun 07 '15 at 08:30
  • I think it's a little bit misleading state that it doesn't matter where you place decoupling capacitors, better to say that physical spacing isn't what's important but rather electrical spacing or better yet impedance. Your article and measurements are trading off a low impedance connection to gain physical spacing. Would you get the same performance if you put your low impedance plane at the bottom of your stack with long vias to your caps and IC, what about 1/4 of vias? I'm not saying your technique is wrong, but it's easy to steer someone wrong like this. – Some Hardware Guy Jun 07 '15 at 15:26
  • @SomeHardwareGuy Given the (closely coupled) pwr/gnd plane pair, this holds. Yes. High or low in the stackup. Caps on one side or the other. Location is not the important thing. If you are talking about 1/4 wavelength stub effect on vias, think about the frequency of interest again. Nowhere near that. But you are right that mounting inductance is important for the individual caps. – Rolf Ostergaard Jun 10 '15 at 05:37
  • Not talking about 1/4 wavelength just 1/4 of the number of vias, and for the plane location there's a difference between putting your closely coupled plane on say layer 2-3 and having a bga and caps on the top then there would be say caps on the bottom, or closely coupled plane on layer 8-9 with parts on the top. I just think it's misleading to tell people it doesn't matter where you place caps since that's the kind of thing someone who doesn't yet understand how all this works would really like to hear. Anyway we can continue in chat if you want rather than cluttering up the comment section – Some Hardware Guy Jun 10 '15 at 13:20