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I am looking for way to limit the output current from a LDO (Vout = 5V) to max. 150mA. I found only this circuit
enter image description here

but the problem with this circuit is the voltage drop Vbe of the transistor Q1 and voltage drop across Rsense are too big. Using a Mosfet can solve the problem with Q1 but voltage across Rsense will still be big. Are there other kinds of circuits that I can look for limiting current while keeping load voltage > 4.9V?

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zud
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  • Can you express "too big" in numbers? What are the limits you are looking for? If you want the voltage across R_load to be bigger, increase VCC (we don't even know what it currently is. Or what transistors you are looking at that produce value of X for drop) – PlasmaHH Mar 24 '15 at 09:33
  • @PlasmaHH Sorry. I added Vout of LDO in the question. It is 5V. – zud Mar 24 '15 at 09:45

2 Answers2

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Another alternative to dealing with the voltage dropped over Rsense (which in your transistor feedback circuit must be ~0.6-0.7V to operate) you should investigate using an Op-amp. You can drop 10 times less voltage over Rsense for the designed current limit, by reducing the size of Rsense by 10, and having an op-amp in non-inverting configuration with a gain of 10 to amplify the voltage built up over Rsense while current flows through it.

Here is how it might look:

schematic

simulate this circuit – Schematic created using CircuitLab

M2 being Q1 in your design, as a low-side current limiting FET using Rsense and it's voltage as the current limiting control signal. The Opamp will sense this value, amplify it by 10 with the shown resistors, and then control the FET as if it was a linear resistor. The issue with this is, your load (shown by R1) may not want a floating ground like this, so you have to be careful.

EDIT: I have fixed the circuit to use negative feedback, so as the voltage over Rsense increases, the output of the op-amp decreases, thus turning off the N channel FET. The FET will be in the linear resistance region so it may get hot while current-limiting. The gate of the FET needs to be above 0V, at least above Vgs(min) to begin conducting. At initial condition, the op-amp should have the FET full on, at 5V(or whatever you power the op-amp with). Once M2 conducts Rsense will begin to build up voltage as the current flows, and the gate voltage will decrease in response. The idea is that the analog feedback reaches an equilibrium state, providing a constant current on the output by dynamically driving the MOSFET gate up/down in response to the load.

The important part here is by using some basic analog feedback to get the same result as if Rsense was large, and controlled a (MOSFET or BJT) transistor's base, using the op-amp in a fairly trivial use-case allows you to have a very small value resistance as a current shunt resistor.

schematic

simulate this circuit EDIT: The above schematic retains the standard way of the voltage over Rsense controlling the base of an NPN transistor, but has an intermediate difference amplifier with a gain of 10 to make only 60-70mV turn on the NPN base rather than needing 600-700mV.

Be aware that if you want a high-side current limit load switch, you will need to use a P channel FET, and they have (a little) more complex control circuits.

KyranF
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  • This circuit does not work in many ways. The top issue is that it cuts off current under low load, exactly the opposite of a current limiter. – rioraxe Mar 25 '15 at 16:06
  • I may have got my signals mixed, perhaps an inverted configuration is needed @rioraxe – KyranF Mar 25 '15 at 16:10
  • @rioraxe or of course, a Pfet – KyranF Mar 25 '15 at 16:10
  • @rioraxe check the edited circuit and explanation. I have kept the low-side FET and inverted the analog feedback so that at no load the FET is fully on, and as load increases the FET is gradually turned off to limit the current. – KyranF Mar 25 '15 at 17:06
  • If you use an inverting amplifier, then the output of OA1 would be negative, so a NFET would never turn on. If you use a PFET, you would still need a negative supply rail for the opamp to work. Also, to get any reasonable accuracy, Vgs threshold needs to stay in a narrow range, but Vgs threshold can change significantly from device to device, from temperature... For example, try looking up the Vgs characteristics in a datasheet... – rioraxe Mar 25 '15 at 20:31
  • @rioraxe surely a single supply 5V and 0V to the opamp would provide 5V to the MOSFET when Rsense has zero current through it, and would reduce in output voltage as Rsense gets more and more current through it? I think i'm missing something, and that's my original design with the non-inverting op-amp should have just gone to a NPN BJT like the original suggested circuit - and the BJT is what linearly controls the FET. – KyranF Mar 25 '15 at 20:51
  • @rioraxe check the second circuit schematic I just put in – KyranF Mar 25 '15 at 21:13
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    That looks like it should work. One more thing -- the opamp TL081 would not work correctly with either inputs or output near the lower supply rail, assuming that is connected to ground, a different opamp is needed. Opamp that the output works all the way near the supply rails is usually labeled "rail-to-rail". Opamp that the inputs work down to the lower supply rail is frequently labeled as "single-supply". – rioraxe Mar 26 '15 at 04:30
  • @rioraxe indeed, it was the default part for circuitlab. I would use a MCP6001 or similar general purpose rail to rail input and output for full control. – KyranF Mar 26 '15 at 15:33
  • @KyranF If he wants low overall voltage drop raather than just in the load side of the regulator then this fails as the output must be below input by Vgs of FET. This can be overcome with a higher gate drive voltage or bu ysing a PFET. Of these the PFET solution is cheap and easy and works well. I'd use it . Also if OA V+ is the same as Vin and OA Vout comes close to V+ then Q1 is not needed. – Russell McMahon Oct 07 '16 at 00:16
  • @RussellMcMahon I agree that a PFET high-side switch solution is the best, and works with more loads than the NFET style method does. – KyranF Oct 07 '16 at 03:24
  • The parasitic capacitor (gate-source) is being charged slowly through R6.

    Instead of R6 I would suggest using NPN transistor like in this circuit. I found the idea of using such BJT circuit instead of resistor from here (open emitter and PNP, I flipped it to open collector and NPN).

    My circuit is not tested, probably will not work because of stability issues. I put comparator because I think that comparators generally are faster than op amps. But I am not sure about frequency compensation, etc.

     – Valentin Stoykov Jan 25 '20 at 19:11
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Have you considered putting the current limit upstream of the regulator? The voltage coming in would need to be one Vbe higher, but the output voltage would be as regulated by the regulator when in normal operation.

Be aware that simple current regulation like this makes the output voltage to drop when current limit is reached. The circuit may be protected from burnt out, but some precaution may be necessary to eliminate unwanted behavior due to low out of spec voltage.

schematic

simulate this circuit – Schematic created using CircuitLab

rioraxe
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