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I'm working on a design with MOSFETs and with the LT4415 device.

The MOSFETs should dissipate an average heat of 0.45 W (with peak at 2 W but just a couple of seconds with several minutes to recover). For the LT4415, the maximum would be 1 W of dissipation (but that should be much smaller 0.2 W , I will measure it during real use, it is hard to predict for now).

I decided to have a pattern of small vias (drill 0.3 mm) on a grid of 1x1 mm2. (I talked already about it in another question.)

Now my actual question is how to choose the type of vias. I can imagine that depends how I will solder the device. For now, I think I will solder them with solder paste and hot air.

Initially, my goal was to use filled vias. I talked with the manufacturer. Like expected, the price is twice higher and that takes much longer to manufacture the board.

So I'm wondering if it is a really bad practice not to fill the vias or to have them plugged. I can understand that vias filled with copper are better for heat conduction than empty vias or vias filled with epoxy. However, does that make sense to try or that doesn't have any chance to work out ?

My guess is that vias will be filled with solder so they may have a decent heat conduction, right ?

I attached some pictures of the design (red = top layer, blue = bottom layer, the hashed area are the respective tstop and bstop layers). Feel free to comment ! Thank you in advance.

MOSFET top MOSFET bottom LTC4415 top LTC4415 bottom

Marmoz
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  • While I'm certainly no expert in these matters, filling the holes with solder should result in very similar performance to filled vias. The only difference is likely to be that pure copper has slightly better thermal conductivity than solder, though that's likely to be negligible at a surface area of 21.8mm^2 – Polynomial Mar 05 '15 at 21:01
  • and my two cents, probably no vias is better than empty vias – Vladimir Cravero Mar 05 '15 at 21:08
  • OK, thank you ! So the question becomes: will the solder flow inside of these vias (drill 0.3 mm)? – Marmoz Mar 05 '15 at 21:15
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    TI has some application notes that are for PowerPAD packages, but much of the information should apply here. See PowerPAD Thermally Enhanced Package and PowerPAD Made Easy. Also PowerPAD Layout Guidelines – Tut Mar 05 '15 at 21:48
  • As Dave says your solder will definitely wick to the back of the board did you check pricing on non conductive fill plate flat? Otherwise you'll end up with a big pool of solder to clean up on the back and no guarantees on how well it's attached. – Some Hardware Guy Mar 05 '15 at 21:55
  • The quotation I got was for vias filled with epoxy. It seems to me that the application notes from TI confirm that it is duable and that the pattern of 0.3 mm vias is the right way to go ! – Marmoz Mar 07 '15 at 05:58

1 Answers1

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When you put unfilled vias in a pad, and then put solder paste on the pad with a stencil, the vias will wick solder away from the pad during reflow, potentially "starving" the joint with the component lead/pad. You'll need to account for the extra solder required, perhaps by making the stencil opening oversize, or by specifying a thicker stencil that will leave a thicker layer of paste behind.

Dave Tweed
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    Thank you for the explanation. I get the boards by the end of next week, I will take into account your comment and keep you posted. I hope I will be able to figure out the right quantity of solder paste ! – Marmoz Mar 07 '15 at 06:01
  • @Marmoz : How did it go? – kando Jan 29 '24 at 15:30