Phase shift a data signal by about 200ns

Question

It would be very nice to be able to insert a little "phase shift" circuit into a data line of mine to shift it by one clock - about 200ns - instead of doing it in software which will be difficult and break compatibility with other hardware which runs the same software. The timing will always be fixed. I was thinking of a series C with parallel R but wasn't sure how if it would phase shift; also, it would remove the DC component which might cause issues with the following logic. The solution needs to be as small and as cheap as possible, ideally involving no "phase shift IC", if such a thing exists.

Answer 1

This sounds like another case of a pre-supposed solution. Explain the problem you are trying to solve one or two levels up. Wanting a delay line is a red flag kludge alert. That doesn't mean there are never good reasons for delays, but that usually when I've seen delays proposed they were results of less than ideal higher level design.

What you apparently want is a delay. This is not the same as a phase shift except at a single frequency. For example, 200ns is a 90 degree phase shift at 1.25MHz. That same 90 degree phase shift at 5MHz is 50ns.

However to answer your question in case there really is a legitimate reason for a delay, you can do this cheaply and simply with a low pass filter between two logic gates. R and C in parallel in the signal path is a high pass filter, not a low pass, although they would not remove the DC component. You want the resistor in series with a digital output followed by a capacitor to ground.

The switching thresholds of digital gates are not well guaranteed. You seem to want something cheap and simple, so maybe that's good enough. The switching thresholds of CMOS gates are usually about half the supply voltage, so you want the R-C filter to decay 1/2 the way to its final value in 200ns. The log(2) = .693, so you want .693 time constants to be 200ns. Therefore

R * C * 0.693= 200ns
R * C = 286ns
R = 286ns / C
C = 286ns / R

One example combination is 2.9 KOhms and 100pF.

If you need more accuracy, then the second gate should be a comparator instead of just a ordinary logic gate. That way the switching threshold is well known and controlled.

Answer 2

Well, there are delay ICs, I remember them for delays in the < 1ns order. edit The Micrel SY89297U has a programmable delay up to 7ns, so you would need 29 of them, but you can fine-tune with 5ps resolution! :-)

The thing with RC is that you won't get the same delay over the full spectrum of your edges, so they will be distorted. You can restore the edge by following the RC with a gate. However, it occurred to me that this will cause jitter if the edges aren't evenly spaced. If an edge is closely followed by another one, the voltage over the cap won't have reached the V+ (GND) yet, and the gate's threshold will be reached sooner. This jitter may considerably reduced if the single RC + gate is replaced by a series of them, with short time constants.

Can't you use a few older CMOS gates (CD4000), they have a typical delay of 60ns, so 3 gates will come close. You can add a pair of low-power Schottky gates to get a better match.

No wait, I've got it! :-) SDL (for Surface Acoustic Wave Delay Line). I've never worked with SAW (Surface Acoustic Wave) devices before, in fact I've never even seen one, but there may be devices which have a delay around 200ns, or SAW filters with a tap at that time.

edit
This one will only work if successive edges in your signal are more than 200ns apart. The idea is to use MMVs to create a new edge 200ns after each existing one, and use an SR-flipflop to reconstruct the signal. You feed the signal to two MMVs (T=200ns), the first one directly, the second one inverted. The first one will time out (falling edge) 200ns after a rising edge of the input signal, the second one will time out 200ns after a falling edge of the signal. From those falling edges create short pulses

and feed them to the set and reset input of the SR-flipflop, resp. You'll have to trim one of the MMVs so that a 50% duty cycle input signal also gives 50% duty cycle at the output.

Answer 3

Maxim do a part from their Dallas range, the DS1100 series. If you can find a local supplier, the DS1100-250 using tap 4 would give 200ns, or the DS1100-500 at tap 2. Whether this is cheap enough for you (around 2.80 GBP at 50 off from RS) I don't know, but it is a single chip solution.

Answer 4

If the data out is synchronous, then we can expect to see something like this:

               ___________________             __________
    DIN ______|________|          |___________|          |______

             _____       _____       _____       _____       ___
    CLK ____|     |_____|     |_____|     |_____|     |_____|       

         ____              ___________             __________
    DOUT ____|____________|           |___________|          |___

and delaying DOUT by one clock period can easily be accomplished like this:

             ______
    DOUT>---|D    Q|---DDLY
            |      |
    CLK>----|>     |
            |______|

yielding:

               ___________________             __________
    DIN ______|________|          |___________|          |______

             _____       _____       _____       _____       ___
    CLK ____|     |_____|     |_____|     |_____|     |_____|       

         ____              ___________             __________
    DOUT ____|____________|     1     |___________|          |___

         _________________             ____________           ___
    DDLY _________________|___________|      1     |_________|

Answer 5

If you want to delay something by one clock, use a D-type flip flop. Simple, cheap, and no concerns about calibration.