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Im trying to drive mosfet's gate with couple of BJTs: S9014 (npn) and S9015 (pnp). They are in half bridge, VCC is 12V. Here is schematic:

Schematics

Input is PWM with frequency of ~70KHz from STM32 micro. I expect PWM from 0 to 12V on output, but strange thing happens instead: connecting 12V to VCC does almost nothing, PWM is still 0-3.3V with weird form and small DC offset (output was connected only to oscilloscope probe).
Question: Is my schematic correct and what is wrong with it?

Grig Betsan
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    Q1 is merely emitter-following your input PWM. What else should you expect? – jonk Mar 10 '18 at 22:43
  • define your goal with Vout output and current limit. You only get Vbe drops from 3.3 giving 0.7 to 2.6 out – Tony Stewart EE75 Mar 10 '18 at 22:50
  • @jonk, I am expecting amplified 0-12V signal on output, how I can achieve this? – Grig Betsan Mar 10 '18 at 23:01
  • @GrigBetsan Not by emitter-following. That's for certain. You will have one BE drop from your MCU voltage rail, at best, at the output. You must modify your topology. And given the 70+ kHz you want, you must start to look more at parasitics, too. 100 kHz isn't hard. But it is moving into the area where lots of other considerations factor in. The slew rates start looking pretty darned fast. – jonk Mar 10 '18 at 23:02
  • V Gain required<4 , level shift required. Wrong topology – Tony Stewart EE75 Mar 10 '18 at 23:06
  • How sharp do you want your edges? If you are modifying the pulse width at this rate, how precise do you need to be? These are serious questions that need to be answered. – jonk Mar 10 '18 at 23:06
  • Ciss must be defined – Tony Stewart EE75 Mar 10 '18 at 23:07
  • @TonyStewart.EEsince'75 Yeah. That too. There exists an unspecified load. That's for sure. Must be remedied. – jonk Mar 10 '18 at 23:07
  • A CMOS level shifter is required with known source RdsOn about 1% of Rdson of driver FETs This takes care of RC time constant and CissRdsOn relationship for power FET – Tony Stewart EE75 Mar 10 '18 at 23:11
  • Gate capacitance will be up to 3nF, I want ~100ns edges, or close to this. I am newbie at EE, especially on BJTs – Grig Betsan Mar 10 '18 at 23:18
  • @GrigBetsan 100ns edges will be ... hard ... with discrete parts. The gate capacitance will be easy. – jonk Mar 10 '18 at 23:26
  • Pulse width shouldn't be very precise. Since I want to use TO-92 packaged BJTs, so current through them should not exceed 250mA, but as far as I understand, 250mA is not sufficient for such sharp edges, right? – Grig Betsan Mar 10 '18 at 23:27
  • taking 10~90% of 12V roughly C dV/dt~3nF 10V/0.1us=Ic=300mA so Rce <=10V/300mA=33 Ohms... So an LM555 may (almost) do it – Tony Stewart EE75 Mar 10 '18 at 23:31
  • @GrigBetsan I was thinking just a smidge higher (at about 350 mA) than Tony points out, but he's right. That's probably where the peak current will be. The good thing is that this only happens at the edges. So the average will be a lot less. But you still have to support the peaks, too. Hand construction is going to be a problem. Providing a local resource for charge will be needed I'm sure (bypass caps.) You are nearing 10 MHz territory so I'd dead-bug the construction. No way would I consider a protoboard. – jonk Mar 10 '18 at 23:35
  • I think edge can be more than 100ns... 400ns I guess, maybe little bit more, but I still don't know how to achieve this – Grig Betsan Mar 10 '18 at 23:36
  • @GrigBetsan I'll give it a shot. I have my type of hammer and saw. Others will have theirs. So you may get different approaches. Choose what makes you feel better if you see more than one approach. – jonk Mar 10 '18 at 23:37

2 Answers2

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Here's a crafted design (except that I kind of ... roughed out ... the speed-up paths.) I am not worried about base oscillation of cascode \$Q_3\$ here, so I didn't do anything for it. It should be fine. If it turns out to be a problem, insert a \$68\:\Omega\$ to \$220\:\Omega\$ resistor between the base of \$Q_3\$ and the \$3.3\:\text{V}\$ supply rail.

schematic

simulate this circuit – Schematic created using CircuitLab

Worst case dissipation of any of the BJTs is probably under \$50\:\text{mW}\$, so they should be fine in open air as TO-92s. Perhaps a \$10^\circ\text{C}\$ rise?

Not shown, but probably needed will be some bypass capacitance -- I'd start with \$100\:\mu\text{F}\$ -- across the emitters of \$Q_1\$ and \$Q_2\$. Use short wiring, keep it tight, and probably use dead-bug style wiring.

Rise and fall times, of the circuit itself, can be kept near \$200\:\text{ns}\$, I believe. I would not expect worse than \$350\:\text{ns}\$, even with junk box parts. However, your MCU will have something to say about it as it's own I/O will slew at a rate of its own, too. But the edges are usually reasonably fast. I suspect this circuit will match up nicely.

jonk
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  • cool! Could you give me a hint what the purpose of C2-R3 is? – Marcus Müller Mar 11 '18 at 00:20
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    @MarcusMüller Just a little speed-up to the base of $Q_2$ to sharpen the falling output edge. They are tricky because they work both ways and slow down the other edge -- though the active BJT wins out anyway. This is why I said I just "cheated" on the top and bottom speed-ups. I really should have sat down and spent more time on both of them. But I didn't want to, so I didn't. But these are used to pull charge out of the BJT, since they are operated "saturated." The cap is sized just big enough to get that job done for the BJTs you choose. – jonk Mar 11 '18 at 00:32
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    ah, that makes sense. Also, looking at what it does explains pretty nicely why dead bug style is preferable – excessive parasitic inductivity would just lead to none of the transistors ever fully switching off – Marcus Müller Mar 11 '18 at 00:41
  • @MarcusMüller That reminded me to add the dead-bug wiring note to the answer, rather than leaving it in comments. Thanks! – jonk Mar 11 '18 at 00:45
  • C1 is a 2.2us hammer driver on the output with 1A into 10 It can be reduced to match the FET requirements and add series R 200 Ohms to PWM input to raise output Rce. Similarily C2 is 70us can be reduced to 100ns – Tony Stewart EE75 Mar 11 '18 at 00:47
  • Also D1 serves no purpose on Q1 but is critical for Q2 due to C2 for a clamp. – Tony Stewart EE75 Mar 11 '18 at 01:02
  • @TonyStewart.EEsince'75 Yes, C1 is a bit overkill. I just wanted to make sure. It could certainly be reduced some. The I/O pins already have a typical 100 Ohm or so. I was assuming that would be present. The negative going voltage on Q2's base probably won't ever cause any zenering. There just isn't enough from the I/O pin to get there. But you make a point about where I put D1. I'll just remove it from the schematic. – jonk Mar 11 '18 at 01:36
  • C1 will dump ~1W pulse into Q1 for the duration of t so it needs a series R ~100 – Tony Stewart EE75 Mar 11 '18 at 01:43
  • @TonyStewart.EEsince'75 Are we talking about the same thing? The speed-up caps, C2 and C3, certainly impact the peak power pulses, which as I've set them will only amount to maybe $400:\text{nJ}$ mean for about $100:\text{ns}$ or so. A series resistor with C1 isn't going to move the power pulses in the two output BJTs much, as I see it. However, those speed-ups are a bit heavy handed I'll grant. But like I said in the post, I didn't work on them much. So I'd like to see your calculations demonstrating the problem in C1 and how a series resistor to C1 changes things. – jonk Mar 11 '18 at 01:56
  • hFE~50 @1A with Q1 driving Ciss =3nF at Vt Ib1=10V/Rsource ~25 Ohms =400mA, so Q1 will current limit >>1A at present If if Source was 100 Ohms which usually not for 3.3Vlogic, Ib1=100mA – Tony Stewart EE75 Mar 11 '18 at 02:03
  • Except Gate R of 10 Ohms limits the current to 1A – Tony Stewart EE75 Mar 11 '18 at 02:10
  • @jonk Your latest Schema is better but still 3.3W(pk) during rise charge assuming fixed 3nF (which it isnt) http://tinyurl.com/y8qvnftj – Tony Stewart EE75 Mar 11 '18 at 02:22
  • @TonyStewart.EEsince'75 I'm shooting for hot edges; the OP wants it. The shoot-through for about $50-100:\text{nS}$ probably could be tweaked better with the speed-ups. ($C_2$ is too big I think by a factor of 3 or so.) But the output BJTs will survive. I didn't add small emitter resistors as I don't think the OP would care. I just put the thing in Spice and include the input I/O pin source resistance and used a $20:\text{ns}$ rise and fall time for the I/O and it looks decent. I think I'll lower $C_3$ to $100:\text{pF}$ though. It's too hot. – jonk Mar 11 '18 at 02:24
  • Looks better now, http://tinyurl.com/y9fmcpy3 but if you edit my source R from 100 to 25 like ARM drivers.. see the effect? – Tony Stewart EE75 Mar 11 '18 at 02:26
  • @TonyStewart.EEsince'75 Edges aren't sharp enough in my opinion. Can you stop that thing and measure the 10% to 90% on both sides? (And while I do like adding BE diodes, in this case I still don't see that the one you added does that much for the OP. I would err on keeping it simple and leaving it out.) – jonk Mar 11 '18 at 02:30
  • use , reset> Run/stop buttons and use cursor to measure edges or Tools options to change sampling rate for more resolution http://tinyurl.com/ybd5fegd – Tony Stewart EE75 Mar 11 '18 at 02:31
  • using a 500kHz clock for convenience to show 50ns rise fall times http://tinyurl.com/yd6w6dnq but more Pd >3Wpk – Tony Stewart EE75 Mar 11 '18 at 02:40
  • Etched and assembled PCB by your last schematic, and I couldn't say it is successful: I burnt my STM32 chip without even powering it on ( I need to be more careful ). IDK why this happened, but I will test and measure later – Grig Betsan Mar 11 '18 at 22:57
  • Cool circuit, what us the purpose of Q3? is this to bias Q1 and Q2's bases wrs to eachother? – Andrew Davis Jul 20 '19 at 08:09
  • @AndrewDavis $Q_3$ is a cascode. In simple terms, the IO pin can "pull down" on its emitter to cause it to have a collector current, which activates $Q_1$. Meanwhile, the IO pin also pulls down on the base of $Q_2$ turning it off. The opposite is when the IO pin is at $3.3:\text{V}$. Then $Q_3$ is off and has no collector current, so $R_4$ pulls $Q_1$ off. Meanwhile, the IO pin pulls up on the base of $Q_2$, turning it on. – jonk Jul 20 '19 at 10:05
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This is just one approach using an LM555 output driver.

There are existing CMOS FET drivers that are better. eg MIC4451 https://www.mouser.com/ds/2/268/mic4451-779120.pdf

enter image description here

Rce is the term I use to define Vol/Iol at 250 mA or (Vcc-Voh)/Ioh

with f(-3dB)=0.35/Tr and Tr=0.1us f-3dB> = 3.5MHz is not too hard with 100V/us slew rate and >250mA peak drive.

Tony Stewart EE75
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