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Referencing this TI inverter as an example part: http://www.ti.com/lit/ds/symlink/sn74ac14.pdf

Specifically, the table at the bottom of page 2 (I would put a picture but I do not know where to upload it). It lists the max Vcc as 6V. It also says the voltage input range is -0.5V to Vcc+0.5V. There is also a note 1 which says "The input and output voltage ratings may be exceeded if the input and output current ratings are observed."

I want to use a Vcc of 3.3V, but I have one input that would be 5V. TI has other inverters that allow 5V inputs with 3.3V Vcc, but their input leakage current is too high for my other inputs. Therefore I am interested in exploring this note.

What does it mean when it says "if the input current rating is observed"? Would this be the input clamp current, Iik (+/- 20 mA)? If so, does that mean I need to put a series resistor in front of the input, so that e.g. 5V - 3.3V = 1.7V (EDIT: and subtract diode drop 0.5V = 1.2V) dropped over the series resistor induces Iik < 20 mA? Should I be concerned about this series resistor being too large, such that the induced current would be less than the input current Ii = +/- 1 uA max?

This question is slightly related to another question on this stackexchange ( Why is it important not to exceed Vcc at the input to a logic gate? ), where one answer off-handedly mentions using resistors to limit input currents, but I would like more detail using a concrete example, especially since this datasheet implies that it's possible to do safely.

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ajs410
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3 Answers3

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The specification means that, provided VDD is kept within bounds and other limits are exceeded, one may source or sink 20mA from any I/O pin without pulling it far enough to damage the part, and one may connect any I/O pin to a rigid voltage between -0.5V and VCC+0.5V without driving enough current through the clamp diodes to damage the part. Note that the only guarantees with regard to pulling an I/O pin beyond the rails are those stated above. In particular, there is no guarantee in the data sheet that pulling a pin even one millivolt beyond the rails won't disrupt the operation of the part--merely that it won't cause permanent damage.

supercat
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Note extremely carefully that note 1 that you refer to in th data sheet applies to the absolute maximum stress only ratings table above the note.
Note that the table below note MUST be what you use for ormal operation.
The normal operation table says that input and output voltgaes both have lower and upper limits of 0V (ground) and vcc respectively during normal operation.

If you violate the spec sheet normal operating conditions requirements you can expect to experience abnormal operating conditions. These may range fro perfectly normal opration through complete maloperation in all cases through to the worst case on unpredicatble possibly unnoticed until something really critical depends on it mis-operation. This can include dying, caching fire or doing anything at all that is not against the laws of Physics under the given circumstances.

The Sparkfun tutorial is generally good but contains one horrendously bad piece of advice,

The Sparkfun resistor and diode solution is safe but pulldown or low is to about 0.6V and pullup is slow compared to a gate switching as the 10k resistor must charge gate an stray input capacitance. These effects often will not matter.

The Sparkfun MOSFET solution is excellent - although the MOSFET used is somewhat marginal at 3V3 gate voltage.

The Sparkfun series 10k resistors in each line is an invitation to disaster and random problems forever.

DON'T DO IT !!!!

enter image description here To maintain the IC in spec sheet limits Vin <= 3V3 so current flow in the 10k resistor = V/R = (5V- 3v3)/10k = 170 microamps.
170 uA is not very much in most normal circumstances + here it is very likely to drive the pin above 3V3. Catch diode conduction begins reasonably noticeably at about 3.8V and is in full swing by 4V. At 4V you can expect about (5-4)/10k = 100 uA. This current will often be injected in the substrate of the IC in places it was never designed to go and can cause parasitic transistor or can latch nodes in existing devices by inpecting charge that cannot dissipate into floating nodes

MANY people argue violently against the above. They say that it is OK to violate spec sheet limits and to inject current into places that it does not belong and that such actions are consistent with good engineering practice. Walk away lowly from such people with your hands in sight.

ADDED

I may have not been clear enough in what I was trying to say.
The table in the datasheet at the bottom of page 2 is headed
"Recommended operating conditions (see Note 3)".
ABOVE the table are notes 1 & 2 BUT they are referenced ONLY in the table above them in mid page headed
"absolute maximum ratings over operating free-air temperature range (unless otherwise noted)".

ie down to the end of note 2 relates to IC survival worst case.
BELOW note 2 relates to IC operation. Nothing in note 2, and above says the IC will OPERATE NORMALLY. Just that it will survive.

Note that this is NOT pedantry - this is how the data sheet is intended to be read but it is not always 100% clear when it is all presented together. Datahseets essentially always start with an abs max survival section and then follow with a recommended section. "Recommended" has min & max values for various parameters and transgressing them means you cannot guarantee correct operation.

In the case of protection diode currents

  • 10 mA will almost garantee disaster and 1 uA will almost guarantee no observable problems.

  • At 1 mA and 10 uA you are likely in trouble and likely OK.

  • At 100 uA and 100 UA (ie they meet) you are in a grey area and anything may happen and sometimes does. It can be random, intermittent and project and sometimes product destroying. Occasionally may be life destroying.

Good engineering and Murphy say that you do not go outside spec sheet min-max range.

Russell McMahon
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  • I would hope the IC was designed so current from a clamping diode doesn't get injected randomly into the body. And the heading says "Abs Max (unless otherwise noted)", so the note leads me to believe that the actual max is excessive Iik for this particular IC. However, you are correct in that you cannot just rely on this without a noted exception. Any potential replacement chip would have to be able to withstand the exact same conditions. – ajs410 Mar 22 '12 at 15:29
  • @ajs410 - You can hope :-). In fact some aspects related to this are designed against in modern ICs. One result is a conditiin called "SCR latchup" where the diode conduction triggers-on a parasitic SCR across the supply. Magic and other smoke can occur and IC destructiin was not uncommon. People have for many years designed in guard rings and other forms of protection to minimise this effect. But that is because the abs max condition is meant to not causeIC destruction. Protection against maloperatioj is less needed as you just set limits that are safe and people don't exceed them. Right ?:-) – Russell McMahon Mar 22 '12 at 15:48
  • Alas, a genration or two have grown up who do not know what "asolute maximum" and "operating" mean, and they will argue at any length to justify what is manifestly really bad and unjustifiable engineering practices. Alas alas a few of these work for IC suppliers and write application notes :-(. These are NOT the IC designers and they can and do put out some utter rubbish on occasion. Caveat emptor etc. – Russell McMahon Mar 22 '12 at 15:50
  • I am not trying to argue at length with you, just pointing out that the datasheet (not an app note) itself says "Absolute Maximum ratings (unless otherwise noted)", and that it is in fact noted. My question really comes down to "is the input current it's talking about Iik?" – ajs410 Mar 22 '12 at 16:13
  • @RussellMcMahon: That probably stems from the fact that many data sheets are written with a huge gap between their page-one advertised features and their defined operating characteristics. If a device claims on page 1 that its pins can source or sink 20mA, and the absolute maximum ratings page gives per-current pin as 20mA, and the only thing Recommended Operating Conditions has to say is that VOL will be 0.5V at 4mA, should an engineer figure or not figure that it should be safe to drive an LED through a resistor that would pass 15mA if the output was grounded to 0V? – supercat Mar 22 '12 at 17:14
  • @RussellMcMahon: I really wish manufacturers would do a better job of explicitly saying what device characteristics should or should not be relied upon. For example, even if a manufacturer couldn't guarantee that putting 20mA through a clamp diode wouldn't disrupt operation, they could probably guarantee some safe level of current; if the part could be disrupted by even a tiny amount of current, they should specify "Recommended conditions: Diode clamping current: 1pA" to make that explicit. – supercat Mar 22 '12 at 17:18
  • @ajs410 - See addition to my answer. – Russell McMahon Mar 23 '12 at 01:43
  • @supercat - The abs max / operating distinction IS usually tightly drawn in black & white. You just need to put on the brain-filters of the writer when reading the spec sheet :-). eg here they DO guarantee some safe current in the operating mode. It is whatever current flows in the catech diodes when the input is anywhere inside the supply range. This usually equals ~~~ 0.0000 uA. ie they spec it in terms of voltage and not current. The current follows. I'd say you were PROBABLY safe to go to about 0.3V outside 0-Vcc range either way and maybe 0.4 and probably not 0.5 BUT maybe not :-). – Russell McMahon Mar 23 '12 at 01:51
  • @RussellMcMahon: If one connects two devices together, a strict precise literal reading of the spec sheets would in many cases demand that even if both devices X and Y are driven from the same supply, one would have to have limiting circuitry on the I/O pins between them, to allow for the fact that X might more current than Y, causing its supply traces to drop an extra millivolt; if Y's output went all the way to its VDD, it could exceed X's VDD by a millivolt or so. Under a strict reading of the datasheet, that would be impermissible. – supercat Mar 23 '12 at 15:48
  • @RussellMcMahon: In practice, with relatively few exceptions, for a device to be unhappy, both voltage and current must exceed certain 'problem' values; limiting either to a safe level would nearly always suffice to keep things happy. – supercat Mar 23 '12 at 15:50
  • @supercat - For body diodes spec sheet always talks in voltage wrt VCC or ground. Current then happens. For most ICs the spec is 0.3V or 0.4V outside rails so interconnection of equal spec pars with a shared supply meets this requirement under normal noise conditions. I agree that noise on a Vcc of any magnitude notionally violates the Vin limit when it is 0-Vcc. This could be overcome by not in fact operating rail to rail, but there is a limit to sensible observance. BUT the limit is not where many people set it. ... – Russell McMahon Mar 24 '12 at 03:35
  • @supercat - Note my suggested rule of thumb currents - / and possible matching effects of 1 10 100 1000 uA. Very very guide only and empirical | 1 uA = vastly unlikely to matter. 10 uA = probably OK. Could cause some effects in eg analog inputs. Other = possible but would be unlucky. 100 uA = "Are you feeling lucky, punk?" ie you can certainly have problems in some cases sometimes. 1 mA = pushing your luck excessively. 10 mA = wall away walk away run ... . | re "unlucky" - Murphy loves to interact with "unlucky". – Russell McMahon Mar 24 '12 at 03:39
  • Nice rules. My point was that many "ROC" are written in such a way that strict compliance would add needless complexity that nobody bothers with. I wonder why manufacturers don't specify ROC rules that would "officially" define a small amount of beyond-the-rails operating tolerance (say 200mv or 100uA), or--for latching logic devices--specify a time allowance between when an upstream part's clock input rises above VIL and a downstream part's clock rises above VIH, assuming parts in the same family, at temperatures within 5C, VDD within 100ms, and manufacture date within a year. – supercat Mar 26 '12 at 13:40
  • Oftentimes, the way propagation and hold-time specs are written, there would be no guarantee that one could safely feed the input to one latch from the output of another, even on the same chip, since minimum propagation time could be zero and required hold time could be positive. In practice, most parts are constructed in such a way that guarantees that outputs won't change until their input is "fully" latched, but I don't know anything in the spec which guarantees that. – supercat Mar 26 '12 at 13:43
  • @RussellMcMahon - I see your edit, and again I understand what you're trying to say. But the way everything is worded ("unless otherwise noted") implies that the input voltage range is actually NOT an absolute maximum rating under certain conditions. I hesitate to mark your answer accepted because it is condescending ("alas, a generation..."), but it is the most thorough answer provided. Next time, I would appreciate if you were less snarky, though. – ajs410 Apr 09 '12 at 22:17
  • ajs410 - Not intending to be rude BUT acceptance of answers is far less important to me than making a wholly valid point. "Alas a generation" is meant to be quaint, not snarky :-). AND it was in a comment and not the answer. AND alas , it's true. Rigour is lacking enough that data sheet wrioters are allowed to do bad things and encourage others. In another area (overdriving LEDs due to sloppy smps designs) I have written to manufacturers who should know better and been ignored. Murphy doesn't care about how we argue - just about how we actually design things :-) – Russell McMahon Apr 10 '12 at 08:47
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This is a nice tutorial on the matter from SparkFun. A 10K resistor between the 5V output and 3.3V input limits the current to something harmless. This only works if your IC has input protection diodes to the rail. Since the "normal" current for CMOS logic is 0, you don't need to worry about your resistor value being too large unless it is so large that the gate capacitance becomes a limiting factor.

The current in question flows from the 5V output, through the series resistor, through the protection diode on the 3.3V pin, and to the 3.3V rail. If your voltage regulator cannot handle reverse current (common) then you should put a shunt resistor between 3V3 and GND to carry away the current.

The neat thing about this method is that it doesn't always work. According to Xilinx, it's OK for their "Spartan 3 and 3E devices with both power and ground diodes" but not for Extended Spartan 3A FPGAs.

joeforker
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  • Does the current flow from 5V rail to 3.3V rail imply that my 3.3V regulator would need to be capable of handling reverse current protection? – ajs410 Mar 21 '12 at 20:19
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    You need to make sure the 3.3V rail will be able to sink the current. Usually, you have other components drawing current from the rail, so it isn't a problem, but some low power circuits draw almost nothing from the rail. You could always add a resistor load to the rail, or a zener diode or something. – markrages Mar 21 '12 at 21:38
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    I've just given this my first ever vote-down - Sorry :-(. I'm afraid this is horrendously bad advice. Please see my answer to see why. It is bad engineering to exceed data sheet normal operting condition limits (does ANYONE here disagree with that statement?) and the datasheet says Vin MUST be between 0V and Vcc during normal operation. in may exceed 0-Vcc by up to 0.6V ONLY when absolute maximum limits are being dealt with. – Russell McMahon Mar 22 '12 at 05:15
  • @markrages I vaguely remembered something from an FPGA datasheet once that talked about this reverse current. Your comment makes sense; so long as there's enough load to sink the reverse current you're okay, because the regulator will just source less current to compensate. But you cannot have so much reverse current that the regulator would need to sink current to compensate, unless its specially designed to do so. – ajs410 Mar 22 '12 at 15:33
  • Here's an FPGA related link on reverse current. http://www.xilinx.com/support/answers/20496.htm Components consuming current could be sorta like Rpar in the link. And the 2.5V rail on Xilinx chips is usually fairly low current as well. – ajs410 Mar 22 '12 at 16:04
  • @ajs410 - alas, it's not the bus pumping up issue which is the problem - that's a problem in its own right, but the fact that if current gets to the 3V3 bus via body diodes it also gets there via the IC subsrate in an undesigned manner. Anything that can happen may happen and sometimes does. – Russell McMahon Mar 22 '12 at 16:19
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    @RussellMcMahon I appreciate your concern, but Xilinx says it's OK for certain devices. Clearly the trick is to determine whether or not you have those devices. Or he could just use a resistor voltage divider. – joeforker Mar 22 '12 at 16:45
  • @joeforker - Any time the datasheet operating specifications section says it is OK that's fine by me. BUT If it is in abs max section or in an application note I would walk away slowly with hands in sight and read the data sheet operating section. Anywhere else is irrelevant. App note writers can produce rubbish and get away with it, and some do. Spec sheet writers can expect to be held to what they say. Xilink chapter and verse would be of interest. – Russell McMahon Mar 23 '12 at 04:24
  • @joeforker - I just removed my down vote, not because I think any differently re the the crucial technical issue involved bu because it's now been well discussed and people can better decide whether to follow the spec sheet or play Russian roulette:-). Can't give you an uo vote though - but I just looked at your other answers and upvoted your SD card wear levelling answer :-). – Russell McMahon Mar 24 '12 at 05:28
  • Its ok, I'm not playing the game for points. – joeforker Mar 24 '12 at 11:44